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2016-09-07ppc: Improve a few more helper flagsBenjamin Herrenschmidt1-7/+7
2016-09-07ppc: Improve the exception helpers flagsBenjamin Herrenschmidt1-2/+2
2016-09-07ppc: Improve flags for helpers loading/writing the time facilitiesBenjamin Herrenschmidt1-21/+21
2016-09-07ppc: Don't generate dead code on unconditional branchesBenjamin Herrenschmidt1-5/+9
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt11-20/+20
2016-09-07target-ppc: add extswsli[.] instructionNikunj A Dadhania1-0/+28
2016-09-07target-ppc: add vsrv instructionVivek Andrew Sha4-0/+20
2016-09-07target-ppc: add vslv instructionVivek Andrew Sha4-0/+20
2016-09-07target-ppc: add vcmpnez[b,h,w][.] instructionsSwapnil Bokade4-0/+54
2016-09-07target-ppc: add vabsdu[b,h,w] instructionsSandipan Das4-3/+39
2016-09-07target-ppc: add dtstsfi[q] instructionsSandipan Das4-0/+71
2016-09-07target-ppc: implement branch-less divd[o][.]Nikunj A Dadhania1-22/+26
2016-09-07target-ppc: implement branch-less divw[o][.]Nikunj A Dadhania1-25/+23
2016-09-07ppc: load/store multiple and string insns don't do LEBenjamin Herrenschmidt1-0/+29
2016-09-07ppc: Use a helper to generate "LE unsupported" alignment interruptsBenjamin Herrenschmidt1-3/+8
2016-09-07ppc: Don't set access_type on all load/stores on hash64Benjamin Herrenschmidt1-1/+3
2016-09-07ppc: Fix CFAR updatesBenjamin Herrenschmidt1-4/+4
2016-09-07ppc: Speed up dcbzBenjamin Herrenschmidt2-28/+29
2016-09-07ppc: Handle unconditional (always/never) traps at translation timeBenjamin Herrenschmidt1-6/+43
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt2-5/+6
2016-09-07ppc: Don't update NIP in dcbz and lscbxBenjamin Herrenschmidt2-8/+5
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt1-2/+1
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt2-10/+4
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt2-7/+6
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt4-14/+5
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt2-22/+13
2016-09-07ppc: Fix source NIP on SLB related interruptsBenjamin Herrenschmidt1-8/+8
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt3-122/+91
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt2-11/+6
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt3-20/+32
2016-09-07ppc: FP exceptions are always preciseBenjamin Herrenschmidt1-5/+6
2016-09-07ppc: Don't update the NIP in floating point generated codeBenjamin Herrenschmidt2-34/+0
2016-09-07ppc: Make float_check_status() pass the return addressBenjamin Herrenschmidt1-27/+40
2016-09-07ppc: Make float_invalid_op_excp() pass the return addressBenjamin Herrenschmidt1-2/+4
2016-09-07ppc: Rename fload_invalid_op_excp to float_invalid_op_excpBenjamin Herrenschmidt1-61/+61
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt3-991/+994
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt3-1065/+1077
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt3-363/+365
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt3-1326/+1336
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt3-1201/+1213
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt2-17/+42
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania2-54/+155
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania1-0/+25
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania1-0/+14
2016-09-07target-ppc: add setb instructionVivek Andrew Sha1-0/+22
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania3-0/+35
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania3-0/+17
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das3-0/+16
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania1-0/+48
2016-09-07target-ppc: add modulo word operationsNikunj A Dadhania1-0/+48
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