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AgeCommit message (Expand)AuthorFilesLines
2016-10-28clean-up: removed duplicate #includesAnand J1-1/+0
2016-10-24exec: move cpu_exec_init() calls to realize functionsLaurent Vivier1-8/+7
2016-09-23target-mips: generate fencesLeon Alrae1-2/+30
2016-09-23target-mips: add 24KEc CPU definitionAndré Draszik1-0/+22
2016-09-16tcg: Merge GETPC and GETRARichard Henderson1-9/+9
2016-07-28target-mips: fix EntryHi.EHINV being cleared on TLB exceptionLeon Alrae1-0/+1
2016-07-21kvm-irqchip: i386: add hook for add/remove virqPeter Xu1-0/+11
2016-07-12Clean up ill-advised or unusual header guardsMarkus Armbruster2-6/+6
2016-07-12target-*: Clean up cpu.h header guardsMarkus Armbruster1-3/+3
2016-07-12Fix confusing argument names in some common functionsSergey Sorokin2-6/+7
2016-07-12target-mips: enable 10-bit ASIDs in I6400 CPULeon Alrae1-1/+1
2016-07-12target-mips: support CP0.Config4.AE bitPaul Burton2-1/+3
2016-07-12target-mips: change ASID type to hold more than 8 bitsPaul Burton4-12/+12
2016-07-12target-mips: add ASID mask field and replace magic valuesPaul Burton4-17/+23
2016-07-12target-mips: replace MIPS64R6-generic with the real I6400 CPU modelLeon Alrae1-11/+9
2016-07-12target-mips: add exception base to MIPS CPULeon Alrae3-4/+13
2016-06-29Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-2/+0
2016-06-29target-*: Don't redefine cpu_exec()Peter Crosthwaite1-2/+0
2016-06-24target-mips: Add FCR31's FS bit definitionAleksandar Markovic1-1/+2
2016-06-24target-mips: Implement FCR31's R/W bitmask and related functionalitiesAleksandar Markovic5-19/+42
2016-06-24target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>Aleksandar Markovic3-48/+461
2016-06-24target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>Aleksandar Markovic1-4/+22
2016-06-24target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSAAleksandar Markovic1-1/+2
2016-06-24softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic6-50/+71
2016-06-20Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' int...Peter Maydell1-0/+1
2016-06-20coccinelle: Remove unnecessary variables for function return valueEduardo Habkost1-3/+1
2016-06-20exec: [tcg] Track which vCPU is performing translation and executionLluís Vilanova1-0/+1
2016-06-16os-posix: include sys/mman.hPaolo Bonzini1-1/+0
2016-06-05target-*: dfilter support for in_asmRichard Henderson1-1/+2
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini7-2/+6
2016-05-19mips: move CP0 functions out of cpu.hPaolo Bonzini2-109/+112
2016-05-19qemu-common: push cpu.h inclusion out of qemu-common.hPaolo Bonzini5-17/+23
2016-05-19hw: move CPU state serialization to migration/cpu.hPaolo Bonzini1-1/+1
2016-05-19target-mips: make cpu-qom.h not target specificPaolo Bonzini2-37/+38
2016-05-18Fix some typos found by codespellStefan Weil1-1/+1
2016-05-13Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160513' into stagingPeter Maydell1-1/+1
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov1-5/+15
2016-05-12tb: consistently use uint32_t for tb->flagsEmilio G. Cota1-1/+1
2016-05-12target-mips: fix call to memset in soft reset codeAurelien Jarno1-1/+1
2016-04-28target-mips: Fix RDHWR exception host PCJames Hogan1-8/+8
2016-03-30target-mips: add MAAR, MAARI registerYongbok Kim6-3/+113
2016-03-30target-mips: use CP0_CHECK for gen_m{f|t}hc0Yongbok Kim1-25/+21
2016-03-30target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae4-12/+100
2016-03-30target-mips: check CP0 enabled for CACHE instruction also in R6Leon Alrae1-0/+1
2016-03-30hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae1-0/+1
2016-03-30target-mips: enable CM GCR in MIPS64R6-generic CPULeon Alrae1-1/+2
2016-03-30hw/mips_malta: add CPS to Malta boardLeon Alrae2-0/+11
2016-03-30target-mips: add CMGCRBase registerYongbok Kim2-1/+20
2016-03-24Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-0/+1
2016-03-23target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUsLeon Alrae3-9/+17
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