diff options
author | Paolo Bonzini <pbonzini@redhat.com> | 2016-03-15 13:49:25 +0100 |
---|---|---|
committer | Paolo Bonzini <pbonzini@redhat.com> | 2016-05-19 13:08:05 +0200 |
commit | 416bf936864f16caad6993b9ebd452fb34f801bd (patch) | |
tree | 405827be726e67ce173a3e0daebe0883902e72d1 /target-mips | |
parent | ffa3a3c6c1e5fc7df0ba7a618018be1260db4b33 (diff) | |
download | qemu-416bf936864f16caad6993b9ebd452fb34f801bd.zip qemu-416bf936864f16caad6993b9ebd452fb34f801bd.tar.gz qemu-416bf936864f16caad6993b9ebd452fb34f801bd.tar.bz2 |
target-mips: make cpu-qom.h not target specific
Make MIPSCPU an opaque type within cpu-qom.h, and move all definitions of
private methods, as well as all type definitions that require knowledge
of the layout to cpu.h. This helps making files independent of NEED_CPU_H
if they only need to pass around CPU pointers.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/cpu-qom.h | 37 | ||||
-rw-r--r-- | target-mips/cpu.h | 38 |
2 files changed, 38 insertions, 37 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 4d6f9de..3f5bf23 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -51,41 +51,6 @@ typedef struct MIPSCPUClass { void (*parent_reset)(CPUState *cpu); } MIPSCPUClass; -/** - * MIPSCPU: - * @env: #CPUMIPSState - * - * A MIPS CPU. - */ -typedef struct MIPSCPU { - /*< private >*/ - CPUState parent_obj; - /*< public >*/ - - CPUMIPSState env; -} MIPSCPU; - -static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) -{ - return container_of(env, MIPSCPU, env); -} - -#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) - -#define ENV_OFFSET offsetof(MIPSCPU, env) - -#ifndef CONFIG_USER_ONLY -extern const struct VMStateDescription vmstate_mips_cpu; -#endif - -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, - int flags); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); -int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - int is_write, int is_user, uintptr_t retaddr); +typedef struct MIPSCPU MIPSCPU; #endif diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 53e8262..c65f84e 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -8,6 +8,7 @@ #define CPUArchState struct CPUMIPSState #include "qemu-common.h" +#include "cpu-qom.h" #include "mips-defs.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" @@ -615,7 +616,42 @@ struct CPUMIPSState { MemoryRegion *itc_tag; /* ITC Configuration Tags */ }; -#include "cpu-qom.h" +/** + * MIPSCPU: + * @env: #CPUMIPSState + * + * A MIPS CPU. + */ +struct MIPSCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUMIPSState env; +}; + +static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) +{ + return container_of(env, MIPSCPU, env); +} + +#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(MIPSCPU, env) + +#ifndef CONFIG_USER_ONLY +extern const struct VMStateDescription vmstate_mips_cpu; +#endif + +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); +void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, + int flags); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + int is_write, int is_user, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |