Age | Commit message (Expand) | Author | Files | Lines |
2016-03-30 | target-mips: add MAAR, MAARI register | Yongbok Kim | 1 | -0/+52 |
2016-03-30 | target-mips: use CP0_CHECK for gen_m{f|t}hc0 | Yongbok Kim | 1 | -25/+21 |
2016-03-30 | target-mips: make ITC Configuration Tags accessible to the CPU | Leon Alrae | 1 | -10/+52 |
2016-03-30 | target-mips: check CP0 enabled for CACHE instruction also in R6 | Leon Alrae | 1 | -0/+1 |
2016-03-30 | hw/mips_malta: add CPS to Malta board | Leon Alrae | 1 | -0/+10 |
2016-03-30 | target-mips: add CMGCRBase register | Yongbok Kim | 1 | -0/+18 |
2016-03-23 | target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs | Leon Alrae | 1 | -0/+1 |
2016-03-01 | tcg: Add type for vCPU pointers | LluĂs Vilanova | 1 | -1/+1 |
2016-02-26 | target-mips: implement R6 multi-threading | Yongbok Kim | 1 | -0/+59 |
2016-02-09 | tcg: Change tcg_global_mem_new_* to take a TCGv_ptr | Richard Henderson | 1 | -12/+13 |
2016-02-03 | log: do not unnecessarily include qom/cpu.h | Paolo Bonzini | 1 | -0/+1 |
2016-01-23 | mips: Clean up includes | Peter Maydell | 1 | -0/+1 |
2016-01-23 | target-mips: Fix ALIGN instruction when bp=0 | Miodrag Dinic | 1 | -1/+10 |
2015-10-30 | target-mips: add SIGRIE instruction | Yongbok Kim | 1 | -1/+11 |
2015-10-30 | target-mips: add PC, XNP reg numbers to RDHWR | Yongbok Kim | 1 | -3/+25 |
2015-10-29 | target-mips: Add enum for BREAK32 | Yongbok Kim | 1 | -1/+2 |
2015-10-28 | target-*: Advance pc after recognizing a breakpoint | Richard Henderson | 1 | -2/+4 |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson | 1 | -43/+5 |
2015-10-07 | tcg: Pass data argument to restore_state_to_opc | Richard Henderson | 1 | -4/+5 |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson | 1 | -1/+6 |
2015-10-07 | target-mips: Add delayed branch state to insn_start | Richard Henderson | 1 | -1/+2 |
2015-10-07 | target-*: Introduce and use cpu_breakpoint_test | Richard Henderson | 1 | -15/+10 |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson | 1 | -3/+2 |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson | 1 | -5/+4 |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson | 1 | -1/+1 |
2015-09-18 | target-mips: improve exception handling | Pavel Dovgaluk | 1 | -191/+174 |
2015-09-18 | target-mips: correct MTC0 instruction on MIPS64 | Leon Alrae | 1 | -11/+7 |
2015-09-18 | target-mips: add missing restriction in DAUI instruction | Leon Alrae | 1 | -1/+3 |
2015-09-18 | target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS | Aurelien Jarno | 1 | -39/+0 |
2015-09-18 | target-mips: get rid of MIPS_DEBUG | Aurelien Jarno | 1 | -605/+19 |
2015-09-18 | target-mips: remove wrong checks for recip.fmt and rsqrt.fmt | Petar Jovanovic | 1 | -4/+2 |
2015-09-18 | target-mips: Use tcg_gen_extrh_i64_i32 | Richard Henderson | 1 | -26/+22 |
2015-08-24 | tcg: Remove tcg_gen_trunc_i64_i32 | Richard Henderson | 1 | -2/+2 |
2015-08-13 | target-mips: simplify LWL/LDL mask generation | Aurelien Jarno | 1 | -8/+6 |
2015-08-04 | target-mips: Copy restrictions from ext/ins to dext/dins | Richard Henderson | 1 | -20/+25 |
2015-08-04 | target-mips: fix semihosting for microMIPS R6 | Leon Alrae | 1 | -3/+7 |
2015-07-15 | target-mips: fix page fault address for LWL/LWR/LDL/LDR | Aurelien Jarno | 1 | -0/+12 |
2015-07-15 | target-mips: fix logically dead code reported by Coverity | Leon Alrae | 1 | -0/+3 |
2015-06-26 | target-mips: microMIPS32 R6 POOL16{A, C} instructions | Yongbok Kim | 1 | -15/+118 |
2015-06-26 | target-mips: microMIPS32 R6 Major instructions | Yongbok Kim | 1 | -17/+45 |
2015-06-26 | target-mips: microMIPS32 R6 POOL32{I, C} instructions | Yongbok Kim | 1 | -6/+21 |
2015-06-26 | target-mips: microMIPS32 R6 POOL32F instructions | Yongbok Kim | 1 | -32/+199 |
2015-06-26 | target-mips: microMIPS32 R6 POOL32A{XF} instructions | Yongbok Kim | 1 | -10/+72 |
2015-06-26 | target-mips: microMIPS32 R6 branches and jumps | Yongbok Kim | 1 | -40/+202 |
2015-06-26 | target-mips: add microMIPS32 R6 opcode enum | Yongbok Kim | 1 | -16/+103 |
2015-06-26 | target-mips: signal RI for removed instructions in microMIPS R6 | Yongbok Kim | 1 | -0/+68 |
2015-06-26 | target-mips: raise RI exceptions when FIR.PS = 0 | Yongbok Kim | 1 | -33/+45 |
2015-06-26 | target-mips: rearrange gen_compute_compact_branch | Yongbok Kim | 1 | -236/+236 |
2015-06-26 | target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP | Yongbok Kim | 1 | -67/+99 |
2015-06-26 | target-mips: remove an unused argument | Yongbok Kim | 1 | -3/+2 |