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| author | Miodrag Dinic <miodrag.dinic@imgtec.com> | 2015-12-03 16:48:57 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-01-23 14:30:04 +0000 |
| commit | 51243852af322f0a1103a90c936c43db84def82f (patch) | |
| tree | c48b75c9bd394803217186b933c258f10f30c955 /target-mips/translate.c | |
| parent | 1aa56f6ee7d2375b0734e98ba69cc41416894bbc (diff) | |
| download | qemu-51243852af322f0a1103a90c936c43db84def82f.zip qemu-51243852af322f0a1103a90c936c43db84def82f.tar.gz qemu-51243852af322f0a1103a90c936c43db84def82f.tar.bz2 | |
target-mips: Fix ALIGN instruction when bp=0
If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.
Taken from the official documentation (pseudo code) :
ALIGN:
tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
tmp = tmp_rt_hi || tmp_rt_lo
GPR[rd] = sign_extend.32(tmp)
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 5626647..d2443d3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4630,7 +4630,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt, t0 = tcg_temp_new(); gen_load_gpr(t0, rt); if (bp == 0) { - tcg_gen_mov_tl(cpu_gpr[rd], t0); + switch (opc) { + case OPC_ALIGN: + tcg_gen_ext32s_tl(cpu_gpr[rd], t0); + break; +#if defined(TARGET_MIPS64) + case OPC_DALIGN: + tcg_gen_mov_tl(cpu_gpr[rd], t0); + break; +#endif + } } else { TCGv t1 = tcg_temp_new(); gen_load_gpr(t1, rs); |