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path: root/include/hw/riscv
AgeCommit message (Expand)AuthorFilesLines
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-0/+2
2021-09-21sifive_u: Connect the SiFive PWM deviceAlistair Francis1-1/+13
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+2
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+1
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-1/+4
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-0/+5
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-8/+8
2021-05-11hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K1-0/+2
2021-05-11riscv: Add initial support for Shakti C machineVijai Kumar K1-0/+73
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+1
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor1-0/+2
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-1/+0
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng1-1/+1
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng1-0/+3
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng1-0/+4
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-3/+3
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-6/+17
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-3/+5
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-3/+5
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-6/+0
2020-12-17riscv: spike: Remove target macro conditionalsAlistair Francis1-6/+0
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+3
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-1/+4
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng1-0/+2
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng1-1/+3
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng1-0/+5
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-0/+3
2020-10-22hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis1-0/+2
2020-10-22hw/riscv: Return the end address of the loaded firmwareAlistair Francis1-4/+4
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-0/+1
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost2-6/+2
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-17/+17
2020-09-18sifive_e: Rename memmap enum constantsEduardo Habkost1-19/+19
2020-09-13Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell13-642/+149
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng1-45/+0
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-77/+0
2020-09-09hw/riscv: Move riscv_htif model to hw/charBin Meng1-59/+0
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-81/+0
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-60/+0
2020-09-09hw/riscv: Move sifive_gpio model to hw/gpioBin Meng3-78/+2
2020-09-09hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2-81/+1
2020-09-09hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2-92/+1
2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng1-71/+0
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+3
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+3
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+7
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+11
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