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path: root/include/hw/riscv
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2020-09-09hw/riscv: Move sifive_e_prci model to hw/miscBin Meng1-71/+0
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+3
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+3
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+7
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng1-0/+4
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng1-0/+20
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng1-0/+88
2020-09-09hw/riscv: hart: Add a new 'resetvec' propertyBin Meng1-0/+1
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost4-8/+8
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost4-8/+16
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost1-19/+19
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel1-2/+7
2020-08-25hw/riscv: spike: Allow creating multiple NUMA socketsAnup Patel1-2/+9
2020-08-25hw/riscv: Add helpers for RISC-V multi-socket NUMA machinesAnup Patel1-0/+113
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel1-5/+7
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-3/+4
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng1-0/+4
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra2-1/+62
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-1/+3
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-0/+2
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+1
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-0/+6
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+1
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng1-0/+19
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng1-0/+3
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng1-3/+4
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis1-0/+13
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis1-0/+3
2020-06-19sifive_e: Support the revB machineAlistair Francis1-0/+1
2020-06-15riscv: Fix type of SiFive[EU]SocState, member parent_objMarkus Armbruster2-2/+2
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis1-0/+68
2020-06-03riscv/boot: Add a missing header includeAlistair Francis1-0/+1
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis1-0/+4
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis1-4/+2
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel1-2/+4
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng1-0/+1
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis1-0/+2
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel1-1/+2
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel1-0/+2
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-1/+2
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis1-0/+3
2019-10-28riscv/virt: Manually define the machineAlistair Francis1-1/+6
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis1-0/+2
2019-10-28riscv/sifive_u: Manually define the machineAlistair Francis1-1/+6
2019-10-28riscv/sifive_u: Add QSPI memory regionAlistair Francis1-0/+1
2019-10-28riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis1-0/+1
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng3-9/+0
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng1-2/+1
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