riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-06-26	hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()	Daniel Henrique Barboza	1	-0/+1
2024-02-21	hw/riscv/virt.h: correct typos	Manos Pitsidianakis	1	-2/+2
2024-01-10	hw/riscv/virt: Update GPEX MMIO related properties	Sunil V L	1	-0/+1
2024-01-10	hw/riscv: virt: Make few IMSIC macros and functions public	Sunil V L	1	-0/+25
2023-03-06	hw/riscv/virt: Enable basic ACPI infrastructure	Sunil V L	1	-0/+1
2023-03-06	hw/riscv/virt: Add memmap pointer to RiscVVirtState	Sunil V L	1	-0/+1
2023-03-06	hw/riscv/virt: Add a switch to disable ACPI	Sunil V L	1	-0/+2
2023-03-06	hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields	Sunil V L	1	-0/+2
2023-01-08	include: Include headers where needed	Markus Armbruster	1	-1/+1
2023-01-06	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	Bin Meng	1	-1/+1
2023-01-06	hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb	Bin Meng	1	-3/+2
2023-01-06	hw/riscv: virt: Remove the redundant ipi-id property	Atish Patra	1	-1/+0
2022-09-07	hw/riscv: virt: fix the plic's address cells	Conor Dooley	1	-0/+1
2022-04-29	hw/riscv: virt: Create a platform bus	Alistair Francis	1	-1/+6
2022-04-29	hw/riscv: virt: Add a machine done notifier	Alistair Francis	1	-0/+1
2022-03-03	hw/riscv: virt: Increase maximum number of allowed CPUs	Anup Patel	1	-1/+1
2022-03-03	hw/riscv: virt: Add optional AIA IMSIC support to virt machine	Anup Patel	1	-3/+14
2022-03-03	hw/riscv: virt: Add optional AIA APLIC support to virt machine	Anup Patel	1	-6/+20
2022-01-08	hw/riscv: virt: Allow support for 32 cores	Alistair Francis	1	-1/+1
2021-10-28	hw/riscv: virt: Don't use a macro for the PLIC configuration	Alistair Francis	1	-1/+0
2021-09-21	hw/riscv: virt: Add optional ACLINT support to virt machine	Anup Patel	1	-0/+2
2021-03-22	hw/riscv: Add fw_cfg support to virt	Asherah Connor	1	-0/+2
2021-03-10	hw/riscv: migrate fdt field to generic MachineState	Alex Bennée	1	-1/+0
2020-12-17	riscv: virt: Remove target macro conditionals	Alistair Francis	1	-6/+0
2020-09-09	Use DECLARE_CHECKER macros	Eduardo Habkost	1	-2/+2
2020-09-09	Move QOM typedefs and add missing includes	Eduardo Habkost	1	-2/+4
2020-08-25	hw/riscv: virt: Allow creating multiple NUMA sockets	Anup Patel	1	-2/+7
2020-02-10	riscv: virt: Use Goldfish RTC device	Anup Patel	1	-0/+2
2019-10-28	riscv/virt: Add the PFlash CFI01 device	Alistair Francis	1	-0/+3
2019-10-28	riscv/virt: Manually define the machine	Alistair Francis	1	-1/+6
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	1	-4/+0
2019-08-16	include: Make headers more self-contained	Markus Armbruster	1	-0/+3
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis	1	-2/+2
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis	1	-1/+1
2018-12-20	hw/riscv/virt: Connect the gpex PCIe	Alistair Francis	1	-1/+12
2018-12-20	hw/riscv/virt: Increase the number of interrupts	Alistair Francis	1	-1/+1
2018-05-06	RISC-V: Make virt header comment title consistent	Michael Clark	1	-1/+1
2018-05-06	RISC-V: Make some header guards more specific	Michael Clark	1	-2/+2
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	1	-5/+0
2018-05-06	RISC-V: Use ROM base address and size from memmap	Michael Clark	1	-2/+0
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	1	-0/+4
2018-03-07	RISC-V VirtIO Machine	Michael Clark	1	-0/+74