riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-03-04	hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value	Bin Meng	1	-1/+1
2021-03-04	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	Bin Meng	1	-0/+3
2021-03-04	hw/riscv: sifive_u: Add QSPI0 controller and connect a flash	Bin Meng	1	-0/+4
2020-10-22	hw/riscv: sifive_u: Allow specifying the CPU	Alistair Francis	1	-0/+1
2020-09-18	sifive_u: Rename memmap enum constants	Eduardo Habkost	1	-17/+17
2020-09-09	hw/riscv: Move sifive_gpio model to hw/gpio	Bin Meng	1	-1/+1
2020-09-09	hw/riscv: Move sifive_u_otp model to hw/misc	Bin Meng	1	-1/+1
2020-09-09	hw/riscv: Move sifive_u_prci model to hw/misc	Bin Meng	1	-1/+1
2020-09-09	hw/riscv: sifive_u: Connect a DMA controller	Bin Meng	1	-0/+11
2020-08-21	hw/riscv: sifive_u: Add a dummy L2 cache controller device	Bin Meng	1	-0/+4
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng	1	-0/+1
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng	1	-0/+6
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	1	-0/+1
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	1	-0/+19
2020-06-15	riscv: Fix type of SiFive[EU]SocState, member parent_obj	Markus Armbruster	1	-1/+1
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng	1	-0/+1
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis	1	-0/+2
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis	1	-0/+2
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis	1	-1/+6
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis	1	-0/+1
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis	1	-0/+1
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	1	-1/+0
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng	1	-2/+1
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng	1	-1/+2
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng	1	-0/+3
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng	1	-2/+2
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng	1	-0/+3
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng	1	-0/+2
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng	1	-1/+5
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng	1	-0/+2
2019-09-17	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	Bin Meng	1	-6/+1
2019-08-16	include: Make headers more self-contained	Markus Armbruster	1	-0/+1
2019-04-04	riscv: plic: Fix incorrect irq calculation	Alistair Francis	1	-2/+2
2018-12-20	sifive_u: Add clock DT node for GEM ethernet	Anup Patel	1	-1/+2
2018-07-05	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device	Alistair Francis	1	-2/+7
2018-07-05	hw/riscv/sifive_u: Create a SiFive U SoC object	Alistair Francis	1	-2/+14
2018-05-06	RISC-V: Remove unused class definitions	Michael Clark	1	-5/+0
2018-05-06	RISC-V: Replace hardcoded constants with enum values	Michael Clark	1	-0/+4
2018-03-07	SiFive Freedom U Series RISC-V Machine	Michael Clark	1	-0/+69