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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:11 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 834e027a3452e1c139c5400cae550c6c5a340b28 (patch) | |
| tree | e3acff6dc4b34ba338ea59ac714951460109b819 /include/hw/riscv/sifive_u.h | |
| parent | a47ef6e93ab2ca1db8d5ecb61fda3c41f926a26b (diff) | |
| download | qemu-834e027a3452e1c139c5400cae550c6c5a340b28.zip qemu-834e027a3452e1c139c5400cae550c6c5a340b28.tar.gz qemu-834e027a3452e1c139c5400cae550c6c5a340b28.tar.bz2 | |
hw/riscv: sifive_u: Connect a DMA controller
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw/riscv/sifive_u.h')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d3c0c00..793000a 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H +#include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" @@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SIFIVEGPIOState gpio; SiFiveUOTPState otp; + SiFivePDMAState dma; CadenceGEMState gem; uint32_t serial; @@ -72,6 +74,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_L2CC, + SIFIVE_U_PDMA, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -108,6 +111,14 @@ enum { SIFIVE_U_GPIO_IRQ13 = 20, SIFIVE_U_GPIO_IRQ14 = 21, SIFIVE_U_GPIO_IRQ15 = 22, + SIFIVE_U_PDMA_IRQ0 = 23, + SIFIVE_U_PDMA_IRQ1 = 24, + SIFIVE_U_PDMA_IRQ2 = 25, + SIFIVE_U_PDMA_IRQ3 = 26, + SIFIVE_U_PDMA_IRQ4 = 27, + SIFIVE_U_PDMA_IRQ5 = 28, + SIFIVE_U_PDMA_IRQ6 = 29, + SIFIVE_U_PDMA_IRQ7 = 30, SIFIVE_U_GEM_IRQ = 0x35 }; |