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path: root/include/hw/riscv/opentitan.h
AgeCommit message (Expand)AuthorFilesLines
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé1-0/+2
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-7/+7
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+1
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-5/+4
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis1-0/+2
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa1-5/+6
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-9/+21
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-1/+3
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis1-3/+3
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+2
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+1
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-1/+4
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-8/+8
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-6/+17
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost1-3/+1
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-2/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-2/+4
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost1-19/+19
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis1-0/+13
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis1-0/+3
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis1-0/+68