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AgeCommit message (Expand)AuthorFilesLines
2024-11-04hw/pci-bridge/cxl-upstream: Add properties to control link speed and widthJonathan Cameron1-0/+4
2023-11-07hw/cxl: Add a switch mailbox CCI functionJonathan Cameron1-0/+1
2023-11-07hw/pci-bridge/cxl_upstream: Move defintion of device to header.Jonathan Cameron1-0/+18
2022-06-09pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron1-0/+12
2022-03-06pci: expose TYPE_XIO3130_DOWNSTREAM nameIgor Mammedov1-0/+15
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost1-3/+1
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost1-2/+2
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost1-2/+4
2019-06-12Supply missing header guardsMarkus Armbruster1-0/+5
2018-02-09Clean up includesMarkus Armbruster1-1/+0
2018-01-24simba: rename PBMPCIBridge and QOM types to reflect simba namingMark Cave-Ayland1-5/+5
2018-01-24apb: split simba PCI bridge into hw/pci-bridge/simba.cMark Cave-Ayland1-0/+38
generated by cgit v1.1 at 2025-01-02 17:10:12 +0000