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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-10-23 17:07:55 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-11-07 03:39:11 -0500 |
| commit | 4a58330343e6a16f6828e225fd0c054c8d1916bd (patch) | |
| tree | 1599e80f9e433c78b55eef06240dd9720b718946 /include/hw/pci-bridge | |
| parent | 2710d49a7c8b9b117a46847c7ace5eb21d48e882 (diff) | |
| download | qemu-4a58330343e6a16f6828e225fd0c054c8d1916bd.zip qemu-4a58330343e6a16f6828e225fd0c054c8d1916bd.tar.gz qemu-4a58330343e6a16f6828e225fd0c054c8d1916bd.tar.bz2 | |
hw/cxl: Add a switch mailbox CCI function
CXL switch CCIs were added in CXL r3.0. They are a PCI function,
identified by class code that provides a CXL mailbox (identical
to that previously defined for CXL type 3 memory devices) over which
various FM-API commands may be used. Whilst the intent of this
feature is enable switch control from a BMC attached to a switch
upstream port, it is also useful to allow emulation of this feature
on the upstream port connected to a host using the CXL devices as
this greatly simplifies testing.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20231023160806.13206-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'include/hw/pci-bridge')
| -rw-r--r-- | include/hw/pci-bridge/cxl_upstream_port.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h index b02aa8f..1263513 100644 --- a/include/hw/pci-bridge/cxl_upstream_port.h +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -11,6 +11,7 @@ typedef struct CXLUpstreamPort { /*< public >*/ CXLComponentState cxl_cstate; + CXLCCI swcci; DOECap doe_cdat; uint64_t sn; } CXLUpstreamPort; |