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AgeCommit message (Expand)AuthorFilesLines
2019-06-17hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boardsPeter Maydell1-0/+7
2019-06-17hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPUPeter Maydell1-0/+4
2019-06-12Supply missing header guardsMarkus Armbruster1-0/+5
2019-06-12Normalize position of header guardMarkus Armbruster3-6/+8
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster5-5/+0
2019-05-24hw/arm/bcm2835: Use object_initialize() on PL011StatePhilippe Mathieu-Daudé1-1/+1
2019-05-24hw/arm/bcm2835: Use TYPE_PL011 instead of hardcoded stringPhilippe Mathieu-Daudé1-0/+1
2019-05-23hw/arm/exynos4210: QOM'ify the Exynos4210 SoCPhilippe Mathieu-Daudé1-2/+7
2019-05-23arm: Rename hw/arm/arm.h to hw/arm/boot.hPeter Maydell12-15/+13
2019-05-23arm: Move system_clock_scale to armv7m_systick.hPeter Maydell1-4/+0
2019-05-13Clean up decorations and whitespace around header guardsMarkus Armbruster2-2/+1
2019-05-07arm: aspeed: Set SDRAM sizeJoel Stanley1-0/+1
2019-05-07hw/arm/virt: Support firmware configuration with -blockdevMarkus Armbruster1-0/+2
2019-04-29hw/devices: Move TI touchscreen declarations into a new headerPhilippe Mathieu-Daudé1-5/+1
2019-04-29hw/arm/smmuv3: Remove SMMUNotifierNodeEric Auger1-6/+2
2019-03-05hw/arm/virt: Dynamic memory map depending on RAM requirementsEric Auger1-0/+1
2019-03-05hw/arm/virt: Split the memory map descriptionEric Auger1-4/+9
2019-03-05hw/arm/virt: Rename highmem IO regionsEric Auger1-4/+4
2019-02-28hw/arm/armsse: Wire up the MHUsPeter Maydell1-1/+2
2019-02-21hw/arm/armsse: Make 0x5... alias region work for per-CPU devicesPeter Maydell1-1/+1
2019-02-21hw/arm/armsse: Allow boards to specify init-svtorPeter Maydell1-0/+3
2019-02-21hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header commentPeter Maydell1-0/+2
2019-02-01arm: Instantiate NRF51 special NVM's and NVMCSteffen Görtz1-0/+2
2019-02-01hw/arm/armsse: Add SSE-200 modelPeter Maydell1-3/+16
2019-02-01hw/arm/armsse: Add CPU_IDENTITY block to SSE-200Peter Maydell1-0/+3
2019-02-01hw/arm/armsse: Add unimplemented-device stub for CPU local control registersPeter Maydell1-0/+1
2019-02-01hw/arm/armsse: Add unimplemented-device stub for cache control registersPeter Maydell1-0/+1
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for PPUsPeter Maydell1-0/+11
2019-02-01hw/arm/armsse: Add unimplemented-device stubs for MHUsPeter Maydell1-0/+3
2019-02-01hw/arm/armsse: Put each CPU in its own cluster objectPeter Maydell1-0/+2
2019-02-01hw/arm/armsse: Give each CPU its own view of memoryPeter Maydell1-0/+10
2019-02-01hw/arm/armsse: Support dual-CPU configurationPeter Maydell1-5/+16
2019-02-01hw/arm/armsse: Make SRAM bank size configurablePeter Maydell1-0/+1
2019-02-01hw/arm/armsse: Make number of SRAM banks parameterisedPeter Maydell1-2/+7
2019-02-01hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell1-2/+2
2019-02-01hw/arm/iotkit: Refactor into abstract base class and subclassPeter Maydell1-5/+17
2019-02-01hw/arm/iotkit: Rename IoTKit to ARMSSEPeter Maydell1-6/+16
2019-02-01armv7m: Pass through start-powered-off CPU propertyPeter Maydell1-0/+1
2019-01-29arm: Stub out NRF51 TWI magnetometer/accelerometer detectionSteffen Görtz2-0/+3
2019-01-22hw/pcmcia: Remove PCMCIACardState from "qemu/typedefs.h"Philippe Mathieu-Daudé1-0/+1
2019-01-07arm: Add Clock peripheral stub to NRF51 SOCSteffen Görtz1-0/+1
2019-01-07arm: Instantiate NRF51 TimersSteffen Görtz1-0/+4
2019-01-07arm: Instantiate NRF51 general purpose I/OSteffen Görtz1-0/+2
2019-01-07arm: Instantiate NRF51 random number generatorSteffen Görtz1-0/+2
2019-01-07arm: Add header to host common definition for nRF51 SOC peripheralsSteffen Görtz1-0/+45
2019-01-07hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controllerPhilippe Mathieu-Daudé1-0/+1
2019-01-07arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clustersLuc Michel1-0/+3
2018-12-13hw/arm: versal: Correct the nr of IRQs to 192Edgar E. Iglesias1-1/+1
2018-12-13hw/arm: versal: Use IRQs 111 - 118 for virtio-mmioEdgar E. Iglesias1-3/+3
2018-12-11qom: make interface types abstractMarc-André Lureau1-4/+1
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