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AgeCommit message (Expand)AuthorFilesLines
3 dayshw/arm/virt: Allow user-creatable SMMUv3 dev instantiationShameer Kolothum1-0/+1
3 dayshw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT buildShameer Kolothum1-0/+1
2025-08-30hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objectsPeter Maydell1-1/+1
2025-07-16Merge tag 'accel-20250715' of https://github.com/philmd/qemu into stagingStefan Hajnoczi1-9/+0
2025-07-15hw/xen/arch_hvm: Unify x86 and ARM variantsPhilippe Mathieu-Daudé1-9/+0
2025-07-15hw/arm/virt-acpi-build: Modify the DSDT ACPI table to enable ACPI PCI hotplugEric Auger1-0/+1
2025-07-08hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxlJonathan Cameron1-0/+4
2025-07-08MAX78000: Add AES to SOCJackson Donaldson1-0/+2
2025-07-08MAX78000: Add TRNG to SOCJackson Donaldson1-0/+2
2025-07-08MAX78000: Add GCR to SOCJackson Donaldson1-0/+2
2025-07-08MAX78000: Add UART to SOCJackson Donaldson1-0/+3
2025-07-08MAX78000: Add ICC to SOCJackson Donaldson1-0/+6
2025-07-08MAX78000: Add MAX78000FTHR MachineJackson Donaldson1-0/+35
2025-07-03hw/arm/aspeed: Add second SPI chip to Aspeed modelEd Tanous1-0/+2
2025-06-13hw/arm: make cpu targeted by arm_load_kernel the primary CPU.Clément Chigot1-0/+3
2025-05-29hw/arm: Add GMAC devices to NPCM8XX SoCHao Wu1-1/+4
2025-05-14hw/arm: Replace TABs for spaces in OMAP board and device codeSantiago Monserrat Campanello3-271/+271
2025-05-06hw/arm: Attach PSPI module to NPCM8XX SoCTim Lee1-0/+2
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam fieldPhilippe Mathieu-Daudé1-1/+0
2025-05-06hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver fieldPhilippe Mathieu-Daudé1-1/+0
2025-05-06hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers fieldPhilippe Mathieu-Daudé1-1/+0
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_its fieldPhilippe Mathieu-Daudé1-1/+0
2025-05-06hw/arm/virt: Remove VirtMachineClass::disallow_affinity_adjustmentPhilippe Mathieu-Daudé1-1/+0
2025-05-06hw/arm/virt: Remove VirtMachineClass::no_pmu fieldPhilippe Mathieu-Daudé1-1/+0
2025-05-05hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoCSteven Lee1-0/+12
2025-05-05hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoCSteven Lee1-0/+14
2025-05-05aspeed: ast27x0: Map unimplemented devices in SoC memorySteven Lee1-0/+6
2025-05-05hw/arm/aspeed: Add support for loading vbootrom image via "-bios"Jamin Lin1-0/+1
2025-05-05hw/arm/aspeed_ast27x0 Introduce vbootrom memory regionJamin Lin1-0/+2
2025-05-05hw/arm: ast27x0: Wire up EHCI controllersTroy Lee1-1/+3
2025-04-23include/system: Move exec/memory.h to system/memory.hRichard Henderson6-6/+6
2025-03-31hw/arm/fsl-imx8mp: Remove unused defineBernhard Beschow1-1/+0
2025-03-31hw/arm/fsl-imx8mp: Derive struct FslImx8mpState from TYPE_SYS_BUS_DEVICEBernhard Beschow1-1/+2
2025-03-23aspeed: Fix maximum number of spi controllerTroy Lee1-1/+1
2025-03-09hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1Jamin Lin1-0/+1
2025-03-09hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two InstancesJamin Lin1-1/+1
2025-03-09aspeed: Remove duplicate typename in AspeedSoCClassCédric Le Goater1-1/+0
2025-03-07hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helperJianChunfu1-0/+6
2025-03-07target/arm: Implement SEL2 physical and virtual timersAlex Bennée1-0/+2
2025-03-07hw/arm/smmu-common: Remove the repeated ttb fieldJianChunfu1-1/+0
2025-02-25hw/arm/fsl-imx8mp: Add on-chip RAMBernhard Beschow1-0/+1
2025-02-25hw/arm/fsl-imx8mp: Add USB supportBernhard Beschow1-0/+12
2025-02-25hw/arm/fsl-imx8mp: Add Ethernet controllerBernhard Beschow1-0/+8
2025-02-25hw/arm/fsl-imx8mp: Implement general purpose timersBernhard Beschow1-0/+11
2025-02-25hw/arm/fsl-imx8mp: Add watchdog supportBernhard Beschow1-0/+7
2025-02-25hw/arm/fsl-imx8mp: Add SPI controllersBernhard Beschow1-0/+8
2025-02-25hw/arm/fsl-imx8mp: Add I2C controllersBernhard Beschow1-0/+11
2025-02-25hw/arm/fsl-imx8mp: Add GPIO controllersBernhard Beschow1-0/+14
2025-02-25hw/arm/fsl-imx8mp: Add PCIe supportBernhard Beschow1-0/+10
2025-02-25hw/arm/fsl-imx8mp: Add USDHC storage controllersBernhard Beschow1-0/+7
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