index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
hw
Age
Commit message (
Expand
)
Author
Files
Lines
4 days
xen/passthrough: use gsi to map pirq when dom0 is PVH
Jiqian Chen
1
-0
/
+60
4 days
Revert "hw/net/net_tx_pkt: Fix overrun in update_sctp_checksum()"
Akihiko Odaki
1
-4
/
+0
5 days
Merge tag 'accel-cpus-20250309' of https://github.com/philmd/qemu into staging
Stefan Hajnoczi
5
-54
/
+196
5 days
cpus: Remove CPUClass::has_work() handler
Philippe Mathieu-Daudé
3
-12
/
+14
5 days
cpus: Introduce SysemuCPUOps::has_work() handler
Philippe Mathieu-Daudé
1
-0
/
+4
5 days
cpus: Un-inline cpu_has_work()
Philippe Mathieu-Daudé
1
-0
/
+6
5 days
hw/acpi: Prefer cached CpuClass over CPU_GET_CLASS() macro
Philippe Mathieu-Daudé
2
-4
/
+3
5 days
cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro
Philippe Mathieu-Daudé
2
-48
/
+26
5 days
cpus: Build cpu_exec_[un]realizefn() methods once
Philippe Mathieu-Daudé
1
-0
/
+26
5 days
cpus: Register VMState per user / system emulation
Philippe Mathieu-Daudé
2
-0
/
+127
5 days
hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address
Jamin Lin
1
-27
/
+27
5 days
hw/arm/aspeed: Add Machine Support for AST2700 A1
Jamin Lin
1
-0
/
+24
5 days
hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1
Jamin Lin
1
-0
/
+79
5 days
hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
Jamin Lin
1
-0
/
+24
5 days
hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances
Jamin Lin
1
-19
/
+39
5 days
hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping
Jamin Lin
1
-27
/
+50
5 days
hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
Jamin Lin
1
-0
/
+2
5 days
hw/intc/aspeed: Add Support for AST2700 INTCIO Controller
Jamin Lin
1
-0
/
+112
5 days
hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
Jamin Lin
2
-15
/
+135
5 days
hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
Jamin Lin
1
-31
/
+39
5 days
hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and r...
Jamin Lin
1
-39
/
+48
5 days
hw/intc/aspeed: Refactor INTC to support separate input and output pin indices
Jamin Lin
2
-42
/
+67
5 days
hw/intc/aspeed: Add support for multiple output pins in INTC
Jamin Lin
2
-1
/
+9
5 days
hw/intc/aspeed: Rename num_ints to num_inpins for clarity
Jamin Lin
2
-15
/
+18
5 days
hw/intc/aspeed: Support different memory region ops
Jamin Lin
1
-1
/
+4
5 days
hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number
Jamin Lin
1
-25
/
+25
5 days
hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
Jamin Lin
2
-8
/
+9
5 days
hw/intc/aspeed: Add object type name to trace events for better debugging
Jamin Lin
2
-25
/
+31
5 days
hw/intc/aspeed: Introduce helper functions for enable and status registers
Jamin Lin
1
-83
/
+108
5 days
hw/intc/aspeed: Reduce regs array size by adding a register sub-region
Jamin Lin
1
-21
/
+29
5 days
hw/intc/aspeed: Support setting different register size
Jamin Lin
1
-17
/
+5
5 days
hw/intc/aspeed: Introduce dynamic allocation for regs array
Jamin Lin
1
-1
/
+11
5 days
hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity
Jamin Lin
1
-19
/
+19
5 days
hw/intc/aspeed: Support setting different memory size
Jamin Lin
1
-1
/
+8
5 days
hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700
Jamin Lin
1
-1
/
+1
5 days
hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO
Jamin Lin
1
-2
/
+9
5 days
hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer for AST2700
Jamin Lin
1
-2
/
+1
5 days
hw/arm/aspeed Update HW Strap Default Values for AST2700
Jamin Lin
1
-2
/
+4
5 days
hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AS...
Jamin Lin
1
-2
/
+1
5 days
hw/misc/aspeed_scu: Skipping dram_init in u-boot
Jamin Lin
1
-0
/
+2
5 days
hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test
Jamin Lin
1
-0
/
+23
5 days
hw/arm/aspeed_ast27x0: Add HACE support for AST2700
Jamin Lin
1
-0
/
+15
5 days
hw/misc/aspeed_hace: Add AST2700 support
Jamin Lin
1
-0
/
+20
5 days
hw/misc/aspeed_hace: Fix coding style
Jamin Lin
1
-4
/
+8
5 days
aspeed: Remove duplicate typename in AspeedSoCClass
Cédric Le Goater
4
-9
/
+4
5 days
aspeed/soc: Support Non-maskable Interrupt for AST2700
Jamin Lin
1
-0
/
+4
6 days
Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into staging
Stefan Hajnoczi
3
-1
/
+3
6 days
exec: Declare tlb_flush*() in 'exec/cputlb.h'
Philippe Mathieu-Daudé
3
-1
/
+3
7 days
Merge tag 'pull-target-arm-20250307' of https://git.linaro.org/people/pmaydel...
Stefan Hajnoczi
7
-25
/
+30
7 days
Merge tag 'pull-request-2025-03-07' of https://gitlab.com/thuth/qemu into sta...
Stefan Hajnoczi
4
-9
/
+76
[prev]
[next]