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2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz1-14/+18
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz1-3/+0
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz1-14/+11
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater2-9/+6
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater3-34/+119
2019-12-17ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater1-1/+4
2019-12-17ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater1-1/+6
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh1-0/+13
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh1-10/+7
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh1-0/+16
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater2-11/+44
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater2-8/+44
2019-12-17ppc/psi: cleanup definitionsCédric Le Goater1-2/+5
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater3-11/+180
2019-12-17ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz1-14/+2
2019-12-17xics: Don't deassert outputsGreg Kurz1-3/+0
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz1-0/+8
2019-12-17spapr: Simplify ovec diffDavid Gibson3-37/+15
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson2-63/+53
2019-12-17spapr: Improve handling of fdt buffer sizeDavid Gibson1-22/+11
2019-12-17spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeoverDavid Gibson1-20/+13
2019-12-17ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy1-1/+1
2019-12-17ppc/pnv: Dump the XIVE NVT tableCédric Le Goater1-0/+64
2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater3-5/+28
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater1-31/+33
2019-12-17ppc/xive: Synthesize interrupt from the saved IPB in the NVTCédric Le Goater1-0/+52
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater1-10/+11
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater3-28/+0
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater3-32/+65
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater2-17/+37
2019-12-17spapr/xive: Configure number of servers in KVMGreg Kurz1-2/+21
2019-12-17spapr/xics: Configure number of servers in KVMGreg Kurz1-2/+19
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz5-9/+16
2019-12-17ppc/xive: Extend the TIMA operation with a XivePresenter parameterCédric Le Goater2-28/+34
2019-12-17ppc/xive: Use the XiveFabric and XivePresenter interfacesCédric Le Goater1-31/+17
2019-12-17ppc/spapr: Implement the XiveFabric interfaceCédric Le Goater1-0/+39
2019-12-17ppc/pnv: Implement the XiveFabric interfaceCédric Le Goater1-0/+35
2019-12-17ppc/xive: Introduce a XiveFabric interfaceCédric Le Goater1-0/+10
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater2-6/+24
2019-12-17ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helperCédric Le Goater1-0/+19
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater1-2/+7
2019-12-17ppc/pnv: Loop on the threads of the chip to find a matching NVTCédric Le Goater1-26/+35
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz1-18/+12
2019-12-17ppc/xive: Implement the XivePresenter interfaceCédric Le Goater3-44/+97
2019-12-17ppc/xive: Introduce a XivePresenter interfaceCédric Le Goater1-9/+17
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater2-20/+33
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater3-0/+116
2019-12-17ipmi: Add support to customize OEM functionsCédric Le Goater1-44/+6
2019-12-17ppc/xive: Check V bit in TM_PULL_POOL_CTXCédric Le Goater1-0/+5
2019-12-17ppc/xive: Introduce OS CAM line helpersCédric Le Goater1-3/+38
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