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AgeCommit message (Expand)AuthorFilesLines
2022-09-27hw/ssi: ibex_spi: update reg addrWilfred Mallawa1-1/+1
2022-09-27hw/ssi: ibex_spi: fixup typos in ibex_spi_hostWilfred Mallawa1-3/+3
2022-06-30aspeed/smc: Fix potential overflowCédric Le Goater1-2/+2
2022-05-02aspeed/smc: Add AST1030 supportSteven Lee1-0/+157
2022-04-22hw/ssi: Add Ibex SPI device modelWilfred Mallawa3-0/+620
2022-03-08aspeed/smc: Fix error logCédric Le Goater1-1/+1
2022-03-08aspeed/smc: Let the SSI core layer define the bus nameCédric Le Goater1-1/+1
2022-03-08aspeed/smc: Rename 'max_peripherals' to 'cs_num_max'Cédric Le Goater1-21/+21
2022-03-08aspeed/smc: Remove 'num_cs' fieldCédric Le Goater1-7/+0
2022-03-08aspeed/smc: Use max number of CE instead of 'num_cs'Cédric Le Goater1-4/+4
2022-03-02migration: Remove load_state_old and minimum_version_id_oldPeter Maydell1-1/+0
2022-02-26aspeed/smc: Add an address mask on segment registersCédric Le Goater1-0/+11
2022-01-28hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controllerFrancisco Iglesias2-0/+1854
2021-10-22aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater1-4/+7
2021-10-12aspeed/smc: Dump address offset in trace eventsCédric Le Goater1-3/+3
2021-10-12aspeed/smc: Introduce a new addr_width() class handlerCédric Le Goater1-7/+12
2021-10-12aspeed/smc: Add default reset valuesCédric Le Goater1-25/+27
2021-10-12aspeed/smc: QOMify AspeedSMCFlashCédric Le Goater1-8/+68
2021-10-12aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'Cédric Le Goater1-15/+15
2021-10-12aspeed/smc: Remove the 'size' attribute from AspeedSMCFlashCédric Le Goater1-3/+2
2021-10-12aspeed/smc: Drop AspeedSMCController structureCédric Le Goater1-383/+478
2021-10-12aspeed/smc: Stop using the model name for the memory regionsCédric Le Goater1-15/+10
2021-10-12aspeed/smc: Introduce aspeed_smc_error() helperCédric Le Goater1-52/+45
2021-10-12aspeed/smc: Add watchdog Control/Status RegistersCédric Le Goater1-1/+18
2021-09-30qbus: Rename qbus_create() to qbus_new()Peter Maydell1-1/+1
2021-05-05Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pul...Peter Maydell3-3/+0
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2021-05-02Do not include sysemu/sysemu.h if it's not really necessaryThomas Huth1-1/+0
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-05-01aspeed/smc: Add extra controls to request DMACédric Le Goater1-7/+67
2021-05-01aspeed/smc: Add a 'features' attribute to the object classCédric Le Goater1-19/+25
2021-05-01hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use aliasPhilippe Mathieu-Daudé1-3/+4
2021-05-01aspeed/smc: Remove unused "sdram-base" propertyCédric Le Goater1-1/+0
2021-05-01aspeed/smc: Use the RAM memory region for DMAsCédric Le Goater1-2/+1
2021-03-10hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spipsXuzhou Cheng1-10/+0
2021-03-10hw/ssi: xilinx_spips: Clean up coding convention issuesXuzhou Cheng1-9/+14
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng3-0/+363
2021-02-02hw/ssi: imx_spi: Correct tx and rx fifo endiannessBin Meng1-5/+2
2021-02-02hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logicBin Meng1-1/+1
2021-02-02hw/ssi: imx_spi: Round up the burst length to be multiple of 8Bin Meng1-1/+16
2021-02-02hw/ssi: imx_spi: Disable chip selects when controller is disabledXuzhou Cheng1-0/+6
2021-02-02hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabledPhilippe Mathieu-Daudé1-4/+9
2021-02-02hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabledPhilippe Mathieu-Daudé1-31/+29
2021-02-02hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register valuePhilippe Mathieu-Daudé1-8/+24
2021-02-02hw/ssi: imx_spi: Remove pointless variable initializationPhilippe Mathieu-Daudé1-2/+0
2021-02-02hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset()Bin Meng1-4/+10
2021-02-02hw/ssi: imx_spi: Use a macro for number of chip selects supportedBin Meng1-2/+2
2021-01-12hw/*: Use type casting for SysBusDevice in NPCM7XXHao Wu1-1/+1
2020-12-10hw/core/stream: Rename StreamSlave as StreamSinkPhilippe Mathieu-Daudé1-1/+1
2020-12-10hw/ssi: Rename SSI 'slave' as 'peripheral'Philippe Mathieu-Daudé3-28/+29
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