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| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | 2022-08-23 16:12:04 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2022-09-27 07:04:38 +1000 |
| commit | 7a426f83c3192db8006ce29abc702dfa2eb00fc8 (patch) | |
| tree | 2f0a6e4f80e34ef252da1de555552c04da63c5bc /hw/ssi | |
| parent | a44558636aed935579701e7805684d1138383c7d (diff) | |
| download | qemu-7a426f83c3192db8006ce29abc702dfa2eb00fc8.zip qemu-7a426f83c3192db8006ce29abc702dfa2eb00fc8.tar.gz qemu-7a426f83c3192db8006ce29abc702dfa2eb00fc8.tar.bz2 | |
hw/ssi: ibex_spi: update reg addr
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220823061201.132342-5-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/ssi')
| -rw-r--r-- | hw/ssi/ibex_spi_host.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 601041d..94d7da9 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -93,7 +93,7 @@ REG32(ERROR_STATUS, 0x30) FIELD(ERROR_STATUS, CMDINVAL, 3, 1) FIELD(ERROR_STATUS, CSIDINVAL, 4, 1) FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1) -REG32(EVENT_ENABLE, 0x30) +REG32(EVENT_ENABLE, 0x34) FIELD(EVENT_ENABLE, RXFULL, 0, 1) FIELD(EVENT_ENABLE, TXEMPTY, 1, 1) FIELD(EVENT_ENABLE, RXWM, 2, 1) |