index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
hw
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2022-05-24
hw/riscv: virt: Fix interrupt parent for dynamic platform devices
Anup Patel
1
-13
/
+12
2022-05-24
hw/riscv/sifive_u: Resolve redundant property accessors
Bernhard Beschow
1
-20
/
+4
2022-05-24
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
Tsukasa OI
3
-4
/
+4
2022-05-24
hw/riscv: Make CPU config error handling generous (virt/spike)
Tsukasa OI
2
-2
/
+2
2022-04-29
hw/riscv: Enable TPM backends
Alistair Francis
2
-0
/
+5
2022-04-29
hw/riscv: virt: Add device plug support
Alistair Francis
1
-0
/
+35
2022-04-29
hw/riscv: virt: Add support for generating platform FDT entries
Alistair Francis
1
-0
/
+19
2022-04-29
hw/riscv: virt: Create a platform bus
Alistair Francis
2
-19
/
+50
2022-04-29
hw/riscv: virt: Add a machine done notifier
Alistair Francis
1
-90
/
+101
2022-04-29
hw/riscv: Don't add empty bootargs to device tree
Bin Meng
4
-4
/
+4
2022-04-29
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
Bin Meng
1
-2
/
+3
2022-04-22
hw/riscv: boot: Support 64bit fdt address.
Dylan Jhong
1
-5
/
+7
2022-04-22
hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
Niklas Cassel
1
-2
/
+8
2022-04-22
hw/riscv: virt: Exit if the user provided -bios in combination with KVM
Ralf Ramsauer
1
-4
/
+10
2022-04-22
riscv: opentitan: Connect opentitan SPI Host
Wilfred Mallawa
1
-4
/
+32
2022-04-06
Remove qemu-common.h include from most units
Marc-André Lureau
1
-1
/
+0
2022-03-03
hw: riscv: opentitan: fixup SPI addresses
Wilfred Mallawa
1
-3
/
+9
2022-03-03
hw/riscv: virt: Increase maximum number of allowed CPUs
Anup Patel
1
-0
/
+10
2022-03-03
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
Anup Patel
2
-81
/
+359
2022-03-03
hw/riscv: virt: Add optional AIA APLIC support to virt machine
Anup Patel
2
-53
/
+239
2022-02-16
hw/riscv: virt: Use AIA INTC compatible string when available
Anup Patel
1
-2
/
+11
2022-01-21
hw/riscv: Remove macros for ELF BIOS image names
Anup Patel
1
-2
/
+2
2022-01-21
hw/riscv: spike: Allow using binary firmware as bios
Anup Patel
1
-16
/
+25
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
2
-26
/
+73
2022-01-21
riscv: opentitan: fixup plic stride len
Wilfred Mallawa
1
-1
/
+1
2022-01-08
hw/riscv: Use error_fatal for SoC realisation
Alistair Francis
4
-4
/
+4
2021-12-20
hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
Jessica Clarke
1
-3
/
+10
2021-12-15
hw: Replace trivial drive_get_next() by drive_get()
Markus Armbruster
2
-2
/
+2
2021-12-15
hw/sd/ssi-sd: Do not create SD card within controller's realize
Markus Armbruster
1
-1
/
+12
2021-10-28
hw/riscv: opentitan: Fixup the PLIC context addresses
Alistair Francis
1
-2
/
+2
2021-10-28
hw/riscv: virt: Use the PLIC config helper function
Alistair Francis
1
-19
/
+1
2021-10-28
hw/riscv: microchip_pfsoc: Use the PLIC config helper function
Alistair Francis
1
-13
/
+1
2021-10-28
hw/riscv: sifive_u: Use the PLIC config helper function
Alistair Francis
1
-13
/
+1
2021-10-28
hw/riscv: boot: Add a PLIC config string function
Alistair Francis
1
-0
/
+25
2021-10-28
hw/riscv: virt: Don't use a macro for the PLIC configuration
Alistair Francis
1
-1
/
+1
2021-10-22
hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+12
2021-10-22
hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+2
2021-10-22
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Bin Meng
1
-4
/
+12
2021-10-22
hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...
Bin Meng
1
-16
/
+20
2021-10-22
hw/riscv: opentitan: Update to the latest build
Alistair Francis
1
-5
/
+17
2021-10-22
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Richard Henderson
1
-1
/
+1
2021-10-22
hw/riscv: virt: Use machine->ram as the system memory
Mingwang Li
1
-4
/
+2
2021-10-07
hw/riscv: shakti_c: Mark as not user creatable
Alistair Francis
1
-0
/
+7
2021-09-21
hw/riscv: opentitan: Correct the USB Dev address
Alistair Francis
1
-1
/
+1
2021-09-21
hw/riscv: virt: Add optional ACLINT support to virt machine
Anup Patel
1
-1
/
+112
2021-09-21
hw/riscv: virt: Re-factor FDT generation
Anup Patel
1
-200
/
+327
2021-09-21
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
Anup Patel
6
-24
/
+44
2021-09-21
hw/intc: Rename sifive_clint sources to riscv_aclint sources
Anup Patel
7
-12
/
+12
[next]