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AgeCommit message (Expand)AuthorFilesLines
2022-06-10hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra1-10/+18
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel1-13/+12
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow1-20/+4
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI3-4/+4
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI2-2/+2
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis2-0/+5
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis1-0/+35
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis1-0/+19
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis2-19/+50
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-90/+101
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng4-4/+4
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng1-2/+3
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong1-5/+7
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel1-2/+8
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer1-4/+10
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-4/+32
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-3/+9
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-0/+10
2022-03-03hw/riscv: virt: Add optional AIA IMSIC support to virt machineAnup Patel2-81/+359
2022-03-03hw/riscv: virt: Add optional AIA APLIC support to virt machineAnup Patel2-53/+239
2022-02-16hw/riscv: virt: Use AIA INTC compatible string when availableAnup Patel1-2/+11
2022-01-21hw/riscv: Remove macros for ELF BIOS image namesAnup Patel1-2/+2
2022-01-21hw/riscv: spike: Allow using binary firmware as biosAnup Patel1-16/+25
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang2-26/+73
2022-01-21riscv: opentitan: fixup plic stride lenWilfred Mallawa1-1/+1
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis4-4/+4
2021-12-20hw/riscv: Use load address rather than entry point for fw_dynamic next_addrJessica Clarke1-3/+10
2021-12-15hw: Replace trivial drive_get_next() by drive_get()Markus Armbruster2-2/+2
2021-12-15hw/sd/ssi-sd: Do not create SD card within controller's realizeMarkus Armbruster1-1/+12
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis1-2/+2
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis1-0/+25
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+1
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ra...Bin Meng1-16/+20
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis1-5/+17
2021-10-22target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson1-1/+1
2021-10-22hw/riscv: virt: Use machine->ram as the system memoryMingwang Li1-4/+2
2021-10-07hw/riscv: shakti_c: Mark as not user creatableAlistair Francis1-0/+7
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel1-1/+112
2021-09-21hw/riscv: virt: Re-factor FDT generationAnup Patel1-200/+327
2021-09-21hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINTAnup Patel6-24/+44
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