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AgeCommit message (Expand)AuthorFilesLines
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng1-2/+0
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-1/+2
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng1-1/+2
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng1-1/+0
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng1-7/+9
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng1-0/+1
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng1-5/+0
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley1-0/+6
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-52/+63
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra1-4/+0
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+3
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-8/+13
2022-10-27riscv: re-randomize rng-seed on rebootJason A. Donenfeld1-0/+3
2022-10-17hw/riscv: set machine->fdt in spike_board_init()Daniel Henrique Barboza1-0/+6
2022-10-17hw/riscv: set machine->fdt in sifive_u_machine_init()Daniel Henrique Barboza1-0/+3
2022-10-14hw/riscv: virt: Enable booting S-mode firmware from pflashSunil V L2-1/+46
2022-10-14hw/riscv: virt: Move create_fw_cfg() prior to loading kernelSunil V L1-7/+7
2022-10-14hw/riscv: Update comment for qtest check in riscv_find_firmware()Bin Meng1-2/+2
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis1-1/+7
2022-09-27hw/riscv: opentitan: Fixup resetvecAlistair Francis1-1/+1
2022-09-07hw/riscv: virt: Add PMU DT node to the device treeAtish Patra1-0/+16
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel1-11/+2
2022-09-07hw/riscv: virt: fix syscon subnode pathsConor Dooley1-2/+2
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley1-0/+2
2022-09-07hw/riscv: virt: fix uart node nameConor Dooley1-1/+1
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley1-6/+61
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa1-4/+8
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza5-8/+5
2022-09-07hw/riscv: virt: pass random seed to fdtJason A. Donenfeld1-0/+6
2022-07-03hw/riscv: boot: Reduce FDT address alignment constraintsAlistair Francis1-2/+2
2022-06-10hw/core/loader: return image sizes as ssize_tJamie Iles1-2/+3
2022-06-10hw/riscv: virt: Generate fw_cfg DT node correctlyAtish Patra1-10/+18
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel1-13/+12
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow1-20/+4
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI3-4/+4
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI2-2/+2
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis2-0/+5
2022-04-29hw/riscv: virt: Add device plug supportAlistair Francis1-0/+35
2022-04-29hw/riscv: virt: Add support for generating platform FDT entriesAlistair Francis1-0/+19
2022-04-29hw/riscv: virt: Create a platform busAlistair Francis2-19/+50
2022-04-29hw/riscv: virt: Add a machine done notifierAlistair Francis1-90/+101
2022-04-29hw/riscv: Don't add empty bootargs to device treeBin Meng4-4/+4
2022-04-29hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionallyBin Meng1-2/+3
2022-04-22hw/riscv: boot: Support 64bit fdt address.Dylan Jhong1-5/+7
2022-04-22hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabledNiklas Cassel1-2/+8
2022-04-22hw/riscv: virt: Exit if the user provided -bios in combination with KVMRalf Ramsauer1-4/+10
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-4/+32
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-3/+9
2022-03-03hw/riscv: virt: Increase maximum number of allowed CPUsAnup Patel1-0/+10
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