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Author
Files
Lines
2023-01-06
hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
Bin Meng
1
-2
/
+0
2023-01-06
hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
Bin Meng
1
-1
/
+2
2023-01-06
hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
Bin Meng
1
-1
/
+2
2023-01-06
hw/riscv: spike: Remove misleading comments
Bin Meng
1
-1
/
+0
2023-01-06
hw/riscv: Sort machines Kconfig options in alphabetical order
Bin Meng
1
-7
/
+9
2023-01-06
hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
Bin Meng
1
-0
/
+1
2023-01-06
hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
Bin Meng
1
-5
/
+0
2023-01-06
hw/{misc, riscv}: pfsoc: add system controller as unimplemented
Conor Dooley
1
-0
/
+6
2023-01-06
hw/riscv: pfsoc: add missing FICs as unimplemented
Conor Dooley
1
-52
/
+63
2023-01-06
hw/riscv: virt: Remove the redundant ipi-id property
Atish Patra
1
-4
/
+0
2023-01-06
hw/riscv/opentitan: add aon_timer base unimpl
Wilfred Mallawa
1
-0
/
+3
2023-01-06
hw/riscv/opentitan: bump opentitan
Wilfred Mallawa
1
-8
/
+13
2022-10-27
riscv: re-randomize rng-seed on reboot
Jason A. Donenfeld
1
-0
/
+3
2022-10-17
hw/riscv: set machine->fdt in spike_board_init()
Daniel Henrique Barboza
1
-0
/
+6
2022-10-17
hw/riscv: set machine->fdt in sifive_u_machine_init()
Daniel Henrique Barboza
1
-0
/
+3
2022-10-14
hw/riscv: virt: Enable booting S-mode firmware from pflash
Sunil V L
2
-1
/
+46
2022-10-14
hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
Sunil V L
1
-7
/
+7
2022-10-14
hw/riscv: Update comment for qtest check in riscv_find_firmware()
Bin Meng
1
-2
/
+2
2022-09-27
hw/riscv: opentitan: Expose the resetvec as a SoC property
Alistair Francis
1
-1
/
+7
2022-09-27
hw/riscv: opentitan: Fixup resetvec
Alistair Francis
1
-1
/
+1
2022-09-07
hw/riscv: virt: Add PMU DT node to the device tree
Atish Patra
1
-0
/
+16
2022-09-07
target/riscv: Use official extension names for AIA CSRs
Anup Patel
1
-11
/
+2
2022-09-07
hw/riscv: virt: fix syscon subnode paths
Conor Dooley
1
-2
/
+2
2022-09-07
hw/riscv: virt: fix the plic's address cells
Conor Dooley
1
-0
/
+2
2022-09-07
hw/riscv: virt: fix uart node name
Conor Dooley
1
-1
/
+1
2022-09-07
hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
Conor Dooley
1
-6
/
+61
2022-09-07
hw/riscv: opentitan: bump opentitan version
Wilfred Mallawa
1
-4
/
+8
2022-09-07
hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
Daniel Henrique Barboza
5
-8
/
+5
2022-09-07
hw/riscv: virt: pass random seed to fdt
Jason A. Donenfeld
1
-0
/
+6
2022-07-03
hw/riscv: boot: Reduce FDT address alignment constraints
Alistair Francis
1
-2
/
+2
2022-06-10
hw/core/loader: return image sizes as ssize_t
Jamie Iles
1
-2
/
+3
2022-06-10
hw/riscv: virt: Generate fw_cfg DT node correctly
Atish Patra
1
-10
/
+18
2022-05-24
hw/riscv: virt: Fix interrupt parent for dynamic platform devices
Anup Patel
1
-13
/
+12
2022-05-24
hw/riscv/sifive_u: Resolve redundant property accessors
Bernhard Beschow
1
-20
/
+4
2022-05-24
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
Tsukasa OI
3
-4
/
+4
2022-05-24
hw/riscv: Make CPU config error handling generous (virt/spike)
Tsukasa OI
2
-2
/
+2
2022-04-29
hw/riscv: Enable TPM backends
Alistair Francis
2
-0
/
+5
2022-04-29
hw/riscv: virt: Add device plug support
Alistair Francis
1
-0
/
+35
2022-04-29
hw/riscv: virt: Add support for generating platform FDT entries
Alistair Francis
1
-0
/
+19
2022-04-29
hw/riscv: virt: Create a platform bus
Alistair Francis
2
-19
/
+50
2022-04-29
hw/riscv: virt: Add a machine done notifier
Alistair Francis
1
-90
/
+101
2022-04-29
hw/riscv: Don't add empty bootargs to device tree
Bin Meng
4
-4
/
+4
2022-04-29
hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
Bin Meng
1
-2
/
+3
2022-04-22
hw/riscv: boot: Support 64bit fdt address.
Dylan Jhong
1
-5
/
+7
2022-04-22
hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled
Niklas Cassel
1
-2
/
+8
2022-04-22
hw/riscv: virt: Exit if the user provided -bios in combination with KVM
Ralf Ramsauer
1
-4
/
+10
2022-04-22
riscv: opentitan: Connect opentitan SPI Host
Wilfred Mallawa
1
-4
/
+32
2022-04-06
Remove qemu-common.h include from most units
Marc-André Lureau
1
-1
/
+0
2022-03-03
hw: riscv: opentitan: fixup SPI addresses
Wilfred Mallawa
1
-3
/
+9
2022-03-03
hw/riscv: virt: Increase maximum number of allowed CPUs
Anup Patel
1
-0
/
+10
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