riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-10-22	hw/riscv: Load the kernel after the firmware	Alistair Francis	1	-1/+2
2020-09-09	target/riscv: cpu: Set reset vector based on the configured property value	Bin Meng	1	-0/+1
2020-08-27	opentitan: Rename memmap enum constants	Eduardo Habkost	1	-42/+42
2020-07-10	error: Eliminate error_propagate() with Coccinelle, part 1	Markus Armbruster	1	-5/+2
2020-07-10	qom: Put name parameter before value / visitor parameter	Markus Armbruster	1	-2/+2
2020-07-10	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster	1	-4/+2
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-15/+14
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	1	-2/+23
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	1	-2/+12
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis	1	-1/+2
2020-06-15	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster	1	-2/+1
2020-06-15	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster	1	-4/+2
2020-06-15	qom: Less verbose object_initialize_child()	Markus Armbruster	1	-2/+1
2020-06-15	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster	1	-3/+2
2020-06-03	riscv: Initial commit of OpenTitan machine	Alistair Francis	1	-0/+184