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AgeCommit message (Expand)AuthorFilesLines
2020-12-10riscv: do not use ram_size globalPaolo Bonzini1-2/+3
2020-12-10ppc: do not use ram_size globalPaolo Bonzini2-3/+3
2020-12-10nios2: do not use ram_size globalPaolo Bonzini1-4/+4
2020-12-10moxie: do not use ram_size globalPaolo Bonzini1-1/+1
2020-12-10mips: do not use ram_size globalPaolo Bonzini2-3/+3
2020-12-10microblaze: do not use ram_size globalPaolo Bonzini1-4/+4
2020-12-10m68k: do not use ram_size globalPaolo Bonzini2-2/+5
2020-12-10i386: do not use ram_size globalPaolo Bonzini5-8/+10
2020-12-10hppa: do not use ram_size globalPaolo Bonzini1-5/+5
2020-12-10cris: do not use ram_size globalPaolo Bonzini3-1/+3
2020-12-10arm: do not use ram_size globalPaolo Bonzini2-6/+7
2020-12-10digic: remove bios_namePaolo Bonzini1-12/+7
2020-12-10sparc: remove bios_namePaolo Bonzini3-5/+3
2020-12-10sh4: remove bios_namePaolo Bonzini1-2/+1
2020-12-10s390: remove bios_namePaolo Bonzini2-7/+4
2020-12-10rx: move BIOS load from MCU to boardPaolo Bonzini2-9/+10
2020-12-10ppc: remove bios_namePaolo Bonzini7-22/+9
2020-12-10moxie: remove bios_namePaolo Bonzini1-3/+3
2020-12-10mips: remove bios_namePaolo Bonzini4-12/+12
2020-12-10m68k: remove bios_namePaolo Bonzini3-11/+7
2020-12-10lm32: remove bios_namePaolo Bonzini1-3/+1
2020-12-10i386: remove bios_namePaolo Bonzini3-12/+9
2020-12-10hppa: remove bios_namePaolo Bonzini1-2/+1
2020-12-10arm: remove bios_namePaolo Bonzini7-14/+15
2020-12-10alpha: remove bios_namePaolo Bonzini1-1/+1
2020-12-10hw/net/xilinx_axienet: Rename StreamSlave as StreamSinkPhilippe Mathieu-Daudé1-12/+12
2020-12-10hw/dma/xilinx_axidma: Rename StreamSlave as StreamSinkPhilippe Mathieu-Daudé1-13/+13
2020-12-10hw/core/stream: Rename StreamSlave as StreamSinkPhilippe Mathieu-Daudé4-37/+37
2020-12-10hw/ssi: Rename SSI 'slave' as 'peripheral'Philippe Mathieu-Daudé12-93/+94
2020-12-10hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals'Philippe Mathieu-Daudé1-26/+27
2020-12-10WHPX: support for the kernel-irqchip on/offSunil Muthuswamy1-2/+4
2020-12-10target/i386: Support up to 32768 CPUs without IRQ remappingDavid Woodhouse2-10/+13
2020-12-10Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20201210' int...Peter Maydell7-8/+423
2020-12-10Merge remote-tracking branch 'remotes/kraxel/tags/microvm-20201210-pull-reque...Peter Maydell3-25/+102
2020-12-10hw/arm/armv7m: Correct typo in QOM object namePeter Maydell1-1/+1
2020-12-10hw/intc/armv7m_nvic: Implement read/write for RAS register blockPeter Maydell1-0/+56
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell1-0/+13
2020-12-10hw/intc/armv7m_nvic: Fix "return from inactive handler" checkPeter Maydell1-27/+32
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell1-8/+18
2020-12-10target/arm: Implement v8.1M REVIDR registerPeter Maydell1-0/+5
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell1-1/+8
2020-12-10hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFaultPeter Maydell2-12/+68
2020-12-10i.MX6ul: Fix bad printf format specifiersAlex Chen1-2/+2
2020-12-10i.MX6: Fix bad printf format specifiersAlex Chen2-11/+11
2020-12-10i.MX31: Fix bad printf format specifiersAlex Chen2-9/+9
2020-12-10i.MX25: Fix bad printf format specifiersAlex Chen1-6/+6
2020-12-10sbsa-ref: allow to use Cortex-A53/57/72 cpusMarcin Juszkiewicz1-3/+20
2020-12-10xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllersVikram Garhwal2-0/+54
2020-12-10hw/net/can: Introduce Xilinx ZynqMP CAN controllerVikram Garhwal5-0/+1173
2020-12-10hw/arm/smmuv3: Fix up L1STD_SPAN decodingKunkun Jiang1-1/+1
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