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path: root/hw/riscv/opentitan.c
AgeCommit message (Expand)AuthorFilesLines
2023-09-29hw/riscv: opentitan: Fixup local variables shadowingAlistair Francis1-1/+1
2023-06-13hw/riscv/opentitan: Correct OpenTitanState parent type/sizePhilippe Mathieu-Daudé1-1/+2
2023-06-13hw/riscv/opentitan: Explicit machine type definitionPhilippe Mathieu-Daudé1-3/+7
2023-06-13hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definitionPhilippe Mathieu-Daudé1-1/+1
2023-06-13hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macroPhilippe Mathieu-Daudé1-12/+9
2023-06-13hw/riscv/opentitan: Rename machine_[class]_init() functionsPhilippe Mathieu-Daudé1-4/+4
2023-03-22*: Add missing includes of qemu/error-report.hRichard Henderson1-0/+1
2023-02-16hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()Daniel Henrique Barboza1-1/+2
2023-02-16hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()Daniel Henrique Barboza1-1/+2
2023-02-07include/hw/riscv/opentitan: update opentitan IRQsWilfred Mallawa1-40/+40
2023-01-20hw/riscv/boot.c: use MachineState in riscv_load_kernel()Daniel Henrique Barboza1-2/+1
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng1-2/+0
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+3
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-8/+13
2022-09-27hw/riscv: opentitan: Expose the resetvec as a SoC propertyAlistair Francis1-1/+7
2022-09-27hw/riscv: opentitan: Fixup resetvecAlistair Francis1-1/+1
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa1-4/+8
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI1-1/+1
2022-04-22riscv: opentitan: Connect opentitan SPI HostWilfred Mallawa1-4/+32
2022-03-03hw: riscv: opentitan: fixup SPI addressesWilfred Mallawa1-3/+9
2022-01-21riscv: opentitan: fixup plic stride lenWilfred Mallawa1-1/+1
2022-01-08hw/riscv: Use error_fatal for SoC realisationAlistair Francis1-1/+1
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis1-2/+2
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis1-5/+17
2021-09-21hw/riscv: opentitan: Correct the USB Dev addressAlistair Francis1-1/+1
2021-09-21hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO linesAlistair Francis1-0/+3
2021-09-21hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-0/+8
2021-07-15hw/riscv: opentitan: Add the flash aliasAlistair Francis1-0/+6
2021-07-15hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis1-0/+3
2021-06-24hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis1-3/+11
2021-05-11hw/riscv: Fix OT IBEX reset vectorAlexander Wagner1-1/+1
2021-05-11hw/opentitan: Update the interrupt layoutAlistair Francis1-4/+4
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2020-12-17riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis1-24/+57
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-1/+2
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-0/+1
2020-08-27opentitan: Rename memmap enum constantsEduardo Habkost1-42/+42
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster1-5/+2
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-2/+2
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster1-4/+2
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis1-2/+23
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis1-2/+12
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis1-1/+2
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster1-2/+1
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster1-4/+2
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster1-2/+1
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster1-3/+2
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