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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-05-20 07:45:06 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-06-13 17:16:29 +1000 |
| commit | 9b29697fefa59431984aed9118e6fc062da0ee10 (patch) | |
| tree | 202f11da64f91704046b51777ccaaa8f068436f2 /hw/riscv/opentitan.c | |
| parent | 89fbbaddfb33556f3f669d40f917c65e75ea6768 (diff) | |
| download | qemu-9b29697fefa59431984aed9118e6fc062da0ee10.zip qemu-9b29697fefa59431984aed9118e6fc062da0ee10.tar.gz qemu-9b29697fefa59431984aed9118e6fc062da0ee10.tar.bz2 | |
hw/riscv/opentitan: Rename machine_[class]_init() functions
Follow QOM style which declares FOO_init() as instance
initializer and FOO_class_init() as class initializer:
rename the OpenTitan machine class/instance init()
accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230520054510.68822-2-philmd@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/opentitan.c')
| -rw-r--r-- | hw/riscv/opentitan.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index bc67876..2d21ee3 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -75,7 +75,7 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, }; -static void opentitan_board_init(MachineState *machine) +static void opentitan_machine_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); const MemMapEntry *memmap = ibex_memmap; @@ -108,17 +108,17 @@ static void opentitan_board_init(MachineState *machine) } } -static void opentitan_machine_init(MachineClass *mc) +static void opentitan_machine_class_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with OpenTitan"; - mc->init = opentitan_board_init; + mc->init = opentitan_machine_init; mc->max_cpus = 1; mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; mc->default_ram_id = "riscv.lowrisc.ibex.ram"; mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; } -DEFINE_MACHINE("opentitan", opentitan_machine_init) +DEFINE_MACHINE("opentitan", opentitan_machine_class_init) static void lowrisc_ibex_soc_init(Object *obj) { |