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2022-05-26spapr: Use address from elf parser for kernel addressAlexey Kardashevskiy1-2/+11
tl;dr: This allows Big Endian zImage booting via -kernel + x-vof=on. QEMU loads the kernel at 0x400000 by default which works most of the time as Linux kernels are relocatable, 64bit and compiled with "-pie" (position independent code). This works for a little endian zImage too. However a big endian zImage is compiled without -pie, is 32bit, linked to 0x4000000 so current QEMU ends up loading it at 0x4400000 but keeps spapr->kernel_addr unchanged so booting fails. This uses the kernel address returned from load_elf(). If the default kernel_addr is used, there is no change in behavior (as translate_kernel_address() takes care of this), which is: LE/BE vmlinux and LE zImage boot, BE zImage does not. If the VM created with "-machine kernel-addr=0,x-vof=on", then QEMU prints a warning and BE zImage boots. Note #1: SLOF (x-vof=off) still cannot boot a big endian zImage as SLOF enables MSR_SF for everything loaded by QEMU and this leads to early crash of 32bit zImage. Note #2: BE/LE vmlinux images set MSR_SF in early boot so these just work; a LE zImage restores MSR_SF after every CI call and we are lucky enough not to crash before the first CI call. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Tested-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220504065536.3534488-1-aik@ozlabs.ru> [danielhb: use PRIx64 instead of lx in warn_report] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-26hw/ppc/e500: Remove unused BINARY_DEVICE_TREE_FILEBernhard Beschow1-1/+0
Commit 28290f37e20cda27574f15be9e9499493e3d0fe8 'PPC: E500: Generate device tree on reset' improved device tree generation and made BINARY_DEVICE_TREE_FILE obsolete. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220505161805.11116-8-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-26pseries: allow setting stdout-path even on machines with a VGAPaolo Bonzini1-4/+8
-machine graphics=off is the usual way to tell the firmware or the OS that the user wants a serial console. The pseries machine however does not support this, and never adds the stdout-path node to the device tree if a VGA device is provided. This is in addition to the other magic behavior of VGA devices, which is to add a keyboard and mouse to the default USB bus. Split spapr->has_graphics in two variables so that the two behaviors can be separated: the USB devices remains the same, but the stdout-path is added even with "-device VGA -machine graphics=off". Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20220507054826.124936-1-pbonzini@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-05-12machine: use QAPI struct for boot configurationPaolo Bonzini4-5/+5
As part of converting -boot to a property with a QAPI type, define the struct and use it throughout QEMU to access boot configuration. machine_boot_parse takes care of doing the QemuOpts->QAPI conversion by hand, for now. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20220414165300.555321-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-09Warn user if the vga flag is passed but no vga device is createdGautam Agrawal1-0/+1
A global boolean variable "vga_interface_created"(declared in softmmu/globals.c) has been used to track the creation of vga interface. If the vga flag is passed in the command line "default_vga"(declared in softmmu/vl.c) variable is set to 0. To warn user, the condition checks if vga_interface_created is false and default_vga is equal to 0. If "-vga none" is passed, this patch will not warn the user regarding the creation of VGA device. The warning "A -vga option was passed but this machine type does not use that option; no VGA device has been created" is logged if vga flag is passed but no vga device is created. This patch has been tested for x86_64, i386, sparc, sparc64 and arm boards. Signed-off-by: Gautam Agrawal <gautamnagrawal@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/581 Message-Id: <20220501122505.29202-1-gautamnagrawal@gmail.com> [thuth: Fix wrong warning with "-device" in some cases as reported by Paolo] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-05target/ppc: Remove msr_pr macroVíctor Colombo2-2/+2
msr_pr macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20hw/ppc: change indentation to spaces from TABsGuo Zhi2-12/+12
There are still some files in the QEMU PPC code base that use TABs for indentation instead of using spaces. The TABs should be replaced so that we have a consistent coding style. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/374 Signed-off-by: Guo Zhi <qtxuning1999@sjtu.edu.cn> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220412021240.2080218-1-qtxuning1999@sjtu.edu.cn> [danielhb: trimmed commit msg to 72 chars per line] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/vof: Fix uninitialized string tracingAlexey Kardashevskiy1-1/+1
There are error paths which do not initialize propname but the trace_exit label prints it anyway. This initializes the problem string. Spotted by Coverity CID 1487241. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220406045013.3610172-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20hw/ppc/ppc405_boards: Initialize g_autofree pointerBernhard Beschow1-2/+2
Resolves the only compiler warning when building a full QEMU under Arch Linux: Compiling C object libqemu-ppc-softmmu.fa.p/hw_ppc_ppc405_boards.c.o In file included from /usr/include/glib-2.0/glib.h:114, from qemu/include/glib-compat.h:32, from qemu/include/qemu/osdep.h:132, from ../src/hw/ppc/ppc405_boards.c:25: ../src/hw/ppc/ppc405_boards.c: In function ‘ref405ep_init’: /usr/include/glib-2.0/glib/glib-autocleanups.h:28:3: warning: ‘filename’ may be used uninitialized in this function [-Wmaybe-uninitialized] 28 | g_free (*pp); | ^~~~~~~~~~~~ ../src/hw/ppc/ppc405_boards.c:265:26: note: ‘filename’ was declared here 265 | g_autofree char *filename; | ^~~~~~~~ Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220405123534.3395-1-shentey@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20spapr: Move nested KVM hypercalls under a TCG only config.Fabiano Rosas1-6/+20
These are the spapr virtual hypervisor implementation of the nested KVM API. They only make sense when running with TCG. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220325221113.255834-3-farosas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20spapr: Move hypercall_register_softmmuFabiano Rosas1-25/+25
I'm moving this because next patch will add more code under the ifdef and it will be cleaner if we keep them together. Also switch the ifdef branches to make it more convenient to add code under CONFIG_TCG in the next patch. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220325221113.255834-2-farosas@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/pnv: Remove useless checks in set_irq handlersCédric Le Goater1-10/+0
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-6-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/pnv: Remove PnvPsiClas::irq_setCédric Le Goater1-17/+6
All devices raising PSI interrupts are now converted to use GPIO lines and the pnv_psi_irq_set() routines have become useless. Drop them. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-5-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/pnv: Remove PnvOCC::psi linkCédric Le Goater2-18/+10
Use an anonymous output GPIO line to connect the OCC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-4-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/pnv: Remove PnvLpcController::psi linkCédric Le Goater3-21/+26
Create an anonymous output GPIO line to connect the LPC device with the PSIHB device and raise the appropriate PSI IRQ line depending on the processor model. A temporary __pnv_psi_irq_set() routine is introduced to handle the transition. It will be removed when all devices raising PSI interrupts are converted to use GPIOs. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-3-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/pnv: Fix PSI IRQ definitionCédric Le Goater1-6/+3
On HW, the PSI and FSP interrupt levels are muxed under the same interrupt number. For coding reasons, an extra IRQ number was introduced to index register values in an array. It increased the count of IRQs which do not fit in the PSI IRQ range anymore. The PSI and FSP interrupts should be modeled with an extra level of GPIO lines but since QEMU does not support them, simply drop the extra number to stay within the IRQ range. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220323072846.1780212-2-clg@kaod.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20ppc/spapr/ddw: Add 2M pagesizeAlexey Kardashevskiy1-0/+1
Recently the LoPAPR spec got a new 2MB pagesize to support in Dynamic DMA Windows API (DDW), this adds the new flag. Linux supports it since https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38727311871 Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-Id: <20220321071945.918669-1-aik@ozlabs.ru> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-04-20hw: Add compat machines for 7.1Cornelia Huck1-2/+13
Add 7.1 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20220316145521.1224083-1-cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau16-16/+0
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-33-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-06Replace qemu_real_host_page variables with inlined functionsMarc-André Lureau2-2/+2
Replace the global variables with inlined helper functions. getpagesize() is very likely annotated with a "const" function attribute (at least with glibc), and thus optimization should apply even better. This avoids the need for a constructor initialization too. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-12-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-04hw/ppc: free env->tb_env in spapr_unrealize_vcpu()Daniel Henrique Barboza2-0/+10
The timebase is allocated during spapr_realize_vcpu() and it's not freed. This results in memory leaks when doing vcpu unplugs: ==636935== ==636935== 144 (96 direct, 48 indirect) bytes in 1 blocks are definitely lost in loss record 6 ,461 of 8,135 ==636935== at 0x4897468: calloc (vg_replace_malloc.c:760) ==636935== by 0x5077213: g_malloc0 (in /usr/lib64/libglib-2.0.so.0.6400.4) ==636935== by 0x507757F: g_malloc0_n (in /usr/lib64/libglib-2.0.so.0.6400.4) ==636935== by 0x93C3FB: cpu_ppc_tb_init (ppc.c:1066) ==636935== by 0x97BC2B: spapr_realize_vcpu (spapr_cpu_core.c:268) ==636935== by 0x97C01F: spapr_cpu_core_realize (spapr_cpu_core.c:337) ==636935== by 0xD4626F: device_set_realized (qdev.c:531) ==636935== by 0xD55273: property_set_bool (object.c:2273) ==636935== by 0xD523DF: object_property_set (object.c:1408) ==636935== by 0xD588B7: object_property_set_qobject (qom-qobject.c:28) ==636935== by 0xD52897: object_property_set_bool (object.c:1477) ==636935== by 0xD4579B: qdev_realize (qdev.c:333) ==636935== This patch adds a cpu_ppc_tb_free() helper in hw/ppc/ppc.c to allow us to free the timebase. This leak is then solved by calling cpu_ppc_tb_free() in spapr_unrealize_vcpu(). Fixes: 6f4b5c3ec590 ("spapr: CPU hot unplug support") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220329124545.529145-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster10-24/+23
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors. This commit only touches allocations with size arguments of the form sizeof(T). Patch created mechanically with: $ spatch --in-place --sp-file scripts/coccinelle/use-g_new-etc.cocci \ --macro-file scripts/cocci-macro-file.h FILES... Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220315144156.1595462-4-armbru@redhat.com> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
2022-03-14ppc/pnv: Remove user-created PHB{3,4,5} devicesCédric Le Goater1-24/+1
On a real system with POWER{8,9,10} processors, PHBs are sub-units of the processor, they can be deactivated by firmware but not plugged in or out like a PCI adapter on a slot. Nevertheless, having user-created PHBs in QEMU seemed to be a good idea for testing purposes : 1. having a limited set of PHBs speedups boot time. 2. it is useful to be able to mimic a partially broken topology you some time have to deal with during bring-up. PowerNV is also used for distro install tests and having libvirt support eases these tasks. libvirt prefers to run the machine with -nodefaults to be sure not to drag unexpected devices which would need to be defined in the domain file without being specified on the QEMU command line. For this reason : 3. -nodefaults should not include default PHBs User-created PHB{3,4,5} devices satisfied all these needs but reality proves to be a bit more complex, internally when modeling such devices, and externally when dealing with the user interface. Req 1. and 2. can be simply addressed differently with a machine option: "phb-mask=<uint>", which QEMU would use to enable/disable PHB device nodes when creating the device tree. For Req 3., we need to make sure we are taking the right approach. It seems that we should expose a new type of user-created PHB device, a generic virtualized one, that libvirt would use and not one depending on the processor revision. This needs more thinking. For now, remove user-created PHB{3,4,5} devices. All the cleanups we did are not lost and they will be useful for the next steps. Fixes: 5bc67b052b51 ("ppc/pnv: Introduce user creatable pnv-phb4 devices") Fixes: 1f6a88fffc75 ("ppc/pnv: Introduce support for user created PHB3 devices") Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220314130514.529931-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-14ppc/pnv: Always create the PHB5 PEC devicesFrederic Barrat1-3/+1
Always create the PECs (PCI Express Controller) for the system. The PECs host the PHBs and we try to find the matching PEC when creating a PHB, so it must exist. It also matches what we do on POWER9 Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - Rewored commit log - Removed dynamic PHB5 ] Message-Id: <20220310155101.294568-3-fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-07osdep: Move memalign-related functions to their own headerPeter Maydell2-0/+2
Move the various memalign-related functions out of osdep.h and into their own header, which we include only where they are used. While we're doing this, add some brief documentation comments. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220226180723.1706285-10-peter.maydell@linaro.org
2022-03-02hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice()Daniel Henrique Barboza1-4/+2
And return the result of g_strdup_printf() directly instead of using the 'path' var. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-15-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter()Daniel Henrique Barboza1-13/+12
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-14-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt()Daniel Henrique Barboza1-6/+4
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-13-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays()Daniel Henrique Barboza1-8/+8
We can get the job done in spapr_numa_write_assoc_lookup_arrays() a bit cleaner: - 'cur_index = int_buf = g_malloc0(..)' is doing a g_malloc0() in the 'int_buf' pointer and making 'cur_index' point to 'int_buf' all in a single line. No problem with that, but splitting into 2 lines is clearer to follow - use g_autofree in 'int_buf' to avoid a g_free() call later on - 'buf_len' is only being used to store the size of 'int_buf' malloc. Remove the var and just use the value in g_malloc0() directly - remove the 'ret' var and just return the result of fdt_setprop() Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-12-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index()Daniel Henrique Barboza1-4/+2
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-11-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new()Daniel Henrique Barboza1-2/+1
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-10-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize()Daniel Henrique Barboza1-3/+1
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-9-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_drc.c: use g_autofree in drc_realize()Daniel Henrique Barboza1-3/+1
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc()Daniel Henrique Barboza1-18/+12
Use g_autoptr() with GArray* and GString* pointers to avoid calling g_free() and the need for the 'out' label. 'drc_name' can also be g_autofreed to avoid a g_free() call at the end of the while() loop. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-7-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties()Daniel Henrique Barboza1-5/+2
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-6-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string()Daniel Henrique Barboza1-4/+3
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-5-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string()Daniel Henrique Barboza1-5/+3
And get rid of the 'out' label since it's now unused. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-4-danielhb413@gmail.com> [ clg: Fixed typo in commit log ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr.c: fail early if no firmware found in machine_init()Daniel Henrique Barboza1-13/+11
The firmware check consists on a file search (qemu_find_file) and load it via load_imag_targphys(). This validation is not dependent on any other machine state but it currently being done at the end of spapr_machine_init(). This means that we can do a lot of stuff and end up failing at the end for something that we can verify right out of the gate. Move this validation to the start of spapr_machine_init() to fail earlier. While we're at it, use g_autofree in the 'filename' pointer. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen()Daniel Henrique Barboza1-5/+2
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220228175004.8862-2-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/xive: Add support for PQ state bits offloadCédric Le Goater1-2/+6
The trigger message coming from a HW source contains a special bit informing the XIVE interrupt controller that the PQ bits have been checked at the source or not. Depending on the value, the IC can perform the check and the state transition locally using its own PQ state bits. The following changes add new accessors to the XiveRouter required to query and update the PQ state bits. This only applies to the PowerNV machine. sPAPR accessors are provided but the pSeries machine should not be concerned by such complex configuration for the moment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)Cédric Le Goater2-6/+30
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB to be consistent with the other interrupt sources of the system. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a HOMER model to POWER10Cédric Le Goater2-0/+84
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridgeCédric Le Goater1-0/+51
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add POWER10 quadsCédric Le Goater1-10/+40
and use a pnv_chip_power10_quad_realize() helper to avoid code duplication with P9. This still needs some refinements on the XSCOM registers handling in PnvQuad. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a OCC model for POWER10Cédric Le Goater2-0/+26
Our OCC model is very mininal and POWER10 can simply reuse the OCC model we introduced for POWER9. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02ppc/pnv: Add a XIVE2 controller to the POWER10 chipCédric Le Goater1-3/+82
The XIVE2 interrupt controller of the POWER10 processor follows the same logic than on POWER9 but the HW interface has been largely reviewed. It has a new register interface, different BARs, extra VSDs, new layout for the XIVE2 structures, and a set of new features which are described below. This is a model of the POWER10 XIVE2 interrupt controller for the PowerNV machine. It focuses primarily on the needs of the skiboot firmware but some initial hypervisor support is implemented for KVM use (escalation). Support for new features will be implemented in time and will require new support from the OS. * XIVE2 BARS The interrupt controller BARs have a different layout outlined below. Each sub-engine has now own its range and the indirect TIMA access was replaced with a set of pages, one per CPU, under the IC BAR: - IC BAR (Interrupt Controller) . 4 pages, one per sub-engine . 128 indirect TIMA pages - TM BAR (Thread Interrupt Management Area) . 4 pages - ESB BAR (ESB pages for IPIs) . up to 1TB - END BAR (ESB pages for ENDs) . up to 2TB - NVC BAR (Notification Virtual Crowd) . up to 128 - NVPG BAR (Notification Virtual Process and Group) . up to 1TB - Direct mapped Thread Context Area (reads & writes) OPAL does not use the grouping and crowd capability. * Virtual Structure Tables XIVE2 adds new tables types and also changes the field layout of the END and NVP Virtualization Structure Descriptors. - EAS - END new layout - NVT was splitted in : . NVP (Processor), 32B . NVG (Group), 32B . NVC (Crowd == P9 block group) 32B - IC for remote configuration - SYNC for cache injection - ERQ for event input queue The setup is slighly different on XIVE2 because the indexing has changed for some of the tables, block ID or the chip topology ID can be used. * XIVE2 features SCOM and MMIO registers have a new layout and XIVE2 adds a new global capability and configuration registers. The lowlevel hardware offers a set of new features among which : - a configurable number of priorities : 1 - 8 - StoreEOI with load-after-store ordering is activated by default - Gen2 TIMA layout - A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility - increase to 24bit for VP number Other features will have some impact on the Hypervisor and guest OS when activated, but this is not required for initial support of the controller. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02hw/ppc/pnv: Determine ns16550's IRQ number from QOM propertyBernhard Beschow1-1/+4
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This resolves one usage of ISADevice::isairq[] which allows it to be removed eventually. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220301220037.76555-6-shentey@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-28rtc: Have event RTC_CHANGE identify the RTC by QOM pathMarkus Armbruster1-1/+3
Event RTC_CHANGE is "emitted when the guest changes the RTC time" (and the RTC supports the event). What if there's more than one RTC? Which one changed? New @qom-path identifies it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <87a6ejnm80.fsf@pond.sub.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-28qapi: Move RTC_CHANGE back out of target schemaPeter Maydell1-1/+1
This commit effectively reverts commit 183e4281a30962, which moved the RTC_CHANGE event to the target schema. That change was an attempt to make the event target-specific to improve introspection, but the event isn't really target-specific: it's machine or device specific. Putting RTC_CHANGE in the target schema with an ifdef list reduces maintainability (by adding an if: list with a long list of targets that needs to be manually updated as architectures are added or removed or as new devices gain the RTC_CHANGE functionality) and increases compile time (by preventing RTC devices which emit the event from being "compile once" rather than "compile once per target", because qapi-events-misc-target.h uses TARGET_* ifdefs, which are poisoned in "compile once" files.) Move RTC_CHANGE back to misc.json. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Message-Id: <20220221192123.749970-2-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-02-21Mark remaining global TypeInfo instances as constBernhard Beschow2-2/+2
More than 1k of TypeInfo instances are already marked as const. Mark the remaining ones, too. This commit was created with: git grep -z -l 'static TypeInfo' -- '*.c' | \ xargs -0 sed -i 's/static TypeInfo/static const TypeInfo/' Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Message-id: 20220117145805.173070-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-07-20 12:17:57 +0000