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2 daysMerge tag 'hw-misc-20250312' of https://github.com/philmd/qemu into stagingStefan Hajnoczi1-0/+1
Misc HW patches - Set correct values for MPC8569E's eSDHC (Zoltan) - Emulate Ricoh RS5C372 RTC device (Bernhard) - Array overflow fixes in SMSC91C111 netdev (Peter) - Fix typo in Xen HVM (Philippe) - Move graphic height/width/depth globals to their own file (Philippe) - Introduce qemu_arch_available() helper (Philippe) - Check fw_cfg's ACPI availability at runtime (Philippe) - Remove virtio-mem dependency on CONFIG_DEVICES (Philippe) - Sort HyperV SYNDBG API definitions (Pierrick) - Remove need for SDHCI_VENDOR_FSL definition (Philippe) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfRXiMACgkQ4+MsLN6t # wN5zFhAAzSW/hZneD8hycKtr9nBlvZSD72cEt+b656OCbTyyucUi1sG4rMPMvHeW # h6HP6xt2SfQxXbec6Y0pWxWUkBOQzk72s0zpttOED3oEspkrId2D+VSsSH1E+QLh # WoG7/hVgz0bDHexWYIDdGufO4no/icwewAKmC5Kp2HbaNxIIHyWlK1+RO69/lCLN # s3qkNesMsQyEWN28ogEMRqyCIG3oJVP76U4TVcdxIiE51WI8sP8/7V2um0AXN68m # IV3INrfVJjGDp501elrUbD3qsYopRdxoMAvwiVojrLXin6xtS+SQjEe/hcNxzM70 # 0IQPp9WWwLjNkeFlAJF4wpwGJttFNHj+5gtH7/YRrP75jt9kAxPXkFw/OFfpVd30 # NYbeFlWDhRL1QPBs+WPBZTrfD7fRmpfMJRLF3/w61+WvnVrshlyDaoCWbR+L329F # uOQFsBdAD7m/lkZ0mHtskS2vkZx7Itn1av4gql7T7/6cE1R7ItKy1HY9UUCtY6Gp # 7V6XrsAE3khg2HY8IcJ73+sPLQn/GxqZFE7PqmAhgcl6RZEFQv8PNrEgFxCEYyuK # KJjx0hRMLoigp0CEclLfOqz2d3knsI8SJbgD4iTYQc02E69lx8a4XS4N8JXoLEdh # 3i/ndwKEFmzwNuqbU0nYsSJDiAO9ejra8O2BXZS/a4pkxC2jtdw= # =VVr6 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 12 Mar 2025 18:12:51 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250312' of https://github.com/philmd/qemu: hw/sd/sdhci: Remove need for SDHCI_VENDOR_IMX definition hw/hyperv/hyperv-proto: Move SYNDBG definitions from target/i386 hw/virtio/virtio-mem: Remove CONFIG_DEVICES include hw/i386/fw_cfg: Check ACPI availability with acpi_builtin() hw/acpi: Introduce acpi_builtin() helper system: Replace arch_type global by qemu_arch_available() helper system: Extract target-specific globals to their own compilation unit hw/xen/hvm: Fix Aarch64 typo hw/net/smc91c111: Don't allow data register access to overrun buffer hw/net/smc91c111: Use MAX_PACKET_SIZE instead of magic numbers hw/net/smc91c111: Sanitize packet length on tx hw/net/smc91c111: Sanitize packet numbers hw/rtc: Add Ricoh RS5C372 RTC emulation hw/sd/sdhci: Set reset value of interrupt registers Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2 daysMerge tag 'pull-vfio-20250311' of https://github.com/legoater/qemu into stagingStefan Hajnoczi1-0/+1
vfio queue: * Fixed endianness of VFIO device state packets * Improved IGD passthrough support with legacy mode * Improved build * Added support for old AMD GPUs (x550) * Updated property documentation # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmfQfQcACgkQUaNDx8/7 # 7KEUNw/+PjFpHrz5muQ8itkbyd36eJJdcxCl+9IPIWfnUfB582epkLcgvWyswGUo # krFTregoRG0PKtgZDtv95owGtVJOgK6XYFadGHiYkvvsb41twOYsP7/SuI+KMiEv # IDFLMvCTyorSIIoEF8i2EexfGPRV1VoWwvBoHgRRmYlzwzXnufjABpoZ0a25DTye # DQ4yhSfqoIh1gOcdL9tPictnZg9OxKr2ePXNdrtymtEIhg3ZobD3Jd8J4WCcsfKT # fxxBO5NsGgA8oM7i02fYN9kgMwqTnVhSAu1wq9PXsbrnNXam+trywAWSO6CjL+rV # ++STWNSrRoHzuotRBr7BzrTpTFyQyfwBWqUT5L4NlhgXB3Xybk+M6Zj08Yva8pjE # w78JQKvKp54gU34AWBW0/J6+u3v+iE8l1Eywx6xueF9Q+YSUDeW9B1LDdjFJryhF # d8j3J+vuglbdsp05D+tVErf5cqFvFDfrjTkXkZNtmx7wky45XS9ZvNazYW1KI3f9 # bg8Wjb7ZujuvxpSjycPRZzdKa8kqSgSZg7fg91Wimiy1Iqe3SZVVWNchLYiPp8Dm # nXMfOEpVHQZ1vzeo7dVWyxu9Y1ujgvUQy8kMa9q2W2S7HQ5Sna79n7eMVJxqZQ4G # m0ETFToOcPPOnZBWgqNOSUlSQncFuIVgNTDvycQ9dMhGorYcBDI= # =Vh0m # -----END PGP SIGNATURE----- # gpg: Signature made Wed 12 Mar 2025 02:12:23 HKT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250311' of https://github.com/legoater/qemu: (21 commits) vfio/pci: Drop debug commentary from x-device-dirty-page-tracking vfio/pci-quirks: Exclude non-ioport BAR from ATI quirk hw/vfio: Compile display.c once hw/vfio: Compile iommufd.c once hw/vfio: Compile more objects once hw/vfio: Compile some common objects once hw/vfio/common: Get target page size using runtime helpers hw/vfio/common: Include missing 'system/tcg.h' header hw/vfio/spapr: Do not include <linux/kvm.h> system: Declare qemu_[min/max]rampagesize() in 'system/hostmem.h' vfio/migration: Use BE byte order for device state wire packets vfio/igd: Fix broken KVMGT OpRegion support vfio/igd: Introduce x-igd-lpc option for LPC bridge ID quirk vfio/igd: Handle x-igd-opregion option in config quirk vfio/igd: Decouple common quirks from legacy mode vfio/igd: Refactor vfio_probe_igd_bar4_quirk into pci config quirk vfio/pci: Add placeholder for device-specific config space quirks vfio/igd: Move LPC bridge initialization to a separate function vfio/igd: Consolidate OpRegion initialization into a single function vfio/igd: Do not include GTT stolen size in etc/igd-bdsm-size ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2 daysMerge tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu ↵Stefan Hajnoczi19-2322/+1353
into staging * Next round of XIVE patches... * tag 'pull-ppc-for-10.0-1-20250311' of https://gitlab.com/npiggin/qemu: (72 commits) docs/system/ppc/amigang.rst: Update for NVRAM emulation ppc/amigaone: Add #defines for memory map constants ppc/amigaone: Add kernel and initrd support ppc/amigaone: Add default environment ppc/amigaone: Implement NVRAM emulation ppc/amigaone: Simplify replacement dummy_fw spapr: Generate random HASHPKEYR for spapr machines target/ppc: Avoid warning message for zero process table entries target/ppc: Wire up BookE ATB registers for e500 family target/ppc: fix timebase register reset state spapr: nested: Add support for reporting Hostwide state counter ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine ppc: Enable 2nd DAWR support on Power10 PowerNV machine hw/ppc/epapr: Do not swap ePAPR magic value hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG ... [Fix __packed macro redefinition on FreeBSD 14 hosts: ../hw/ppc/pnv_occ.c:397:9: error: '__packed' macro redefined [-Werror,-Wmacro-redefined] 397 | #define __packed QEMU_PACKED | ^ /usr/include/sys/cdefs.h:217:9: note: previous definition is here 217 | #define __packed __attribute__((__packed__)) | ^ --Stefan] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
4 dayshw/sd/sdhci: Set reset value of interrupt registersBALATON Zoltan1-0/+1
The interrupt enable registers are not reset to 0 on Freescale eSDHC but some bits are enabled on reset. At least some U-Boot versions seem to expect this and not initialise these registers before expecting interrupts. Use existing vendor property for Freescale eSDHC and set the reset value of the interrupt registers to match Freescale documentation. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4 dayssystem: Declare qemu_[min/max]rampagesize() in 'system/hostmem.h'Philippe Mathieu-Daudé1-0/+1
Both qemu_minrampagesize() and qemu_maxrampagesize() are related to host memory backends, having the following call stack: qemu_minrampagesize() -> find_min_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) qemu_maxrampagesize() -> find_max_backend_pagesize() -> object_dynamic_cast(obj, TYPE_MEMORY_BACKEND) Having TYPE_MEMORY_BACKEND defined in "system/hostmem.h": include/system/hostmem.h:23:#define TYPE_MEMORY_BACKEND "memory-backend" Move their prototype declaration to "system/hostmem.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-Id: <20250308230917.18907-7-philmd@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250311085743.21724-2-philmd@linaro.org Signed-off-by: Cédric Le Goater <clg@redhat.com>
4 daysppc/amigaone: Add #defines for memory map constantsBALATON Zoltan1-6/+14
Suggested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <3b8e54ad9220d57e7b0a33f3570e880f26677ce8.1740673173.git.balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/amigaone: Add kernel and initrd supportBALATON Zoltan1-1/+112
Add support for -kernel, -initrd and -append command line options. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <489b1be5d95d5153e924c95b0691b8b53f9ffb9e.1740673173.git.balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/amigaone: Add default environmentBALATON Zoltan1-1/+36
Initialise empty NVRAM with default values. This also enables IDE UDMA mode in AmigaOS that is faster but has to be enabled in environment due to problems with real hardware but that does not affect emulation so we can use faster defaults here. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <4d63f88191612329e0ca8102c7c0d4fc626dc372.1740673173.git.balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/amigaone: Implement NVRAM emulationBALATON Zoltan1-3/+110
The board has a battery backed NVRAM where U-Boot environment is stored which is also accessed by AmigaOS and e.g. C:NVGetVar command crashes without it having at least a valid checksum. [npiggin: 32-bit compile fix] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <7e4c0107ef6bdc2b20fb1e780a188275c7dc1e49.1740673173.git.balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/amigaone: Simplify replacement dummy_fwBALATON Zoltan1-4/+1
There's no need to do shift in a loop, doing it in one instruction works just as well, only the result is used. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <446bf740cbb99422be2cc5a31e51a1034eddded7.1740673173.git.balaton@eik.bme.hu> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysspapr: Generate random HASHPKEYR for spapr machinesNicholas Piggin2-0/+5
The hypervisor is expected to create a value for the HASHPKEY SPR for each partition. Currently it uses zero for all partitions, use a random number instead, which in theory might make kernel ROP protection more secure. Signed-of-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241219034035.1826173-4-npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daystarget/ppc: fix timebase register reset stateNicholas Piggin1-3/+8
(H)DEC and PURR get reset before icount does, which causes them to be skewed and not match the init state. This can cause replay to not match the recorded trace exactly. For DEC and HDEC this is usually not noticable since they tend to get programmed before affecting the target machine. PURR has been observed to cause replay bugs when running Linux. Fix this by resetting using a time of 0. Message-ID: <20241219034035.1826173-2-npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysspapr: nested: Add support for reporting Hostwide state counterVaibhav Jain1-33/+86
Add support for reporting Hostwide state counters for nested KVM pseries guests running with 'cap-nested-papr' on Qemu-TCG acting as L0-hypervisor. The Hostwide state counters are statistics about state that L0-hypervisor maintains for the L2-guests and represent the state of all L2-guests, not just a specific one. These stats counters are exposed to L1-Hypervisor by the L0-Hypervisor via a new bit-flag named 'getHostWideState' for the H_GUEST_GET_STATE hcall which is documented at [1]. Once this flag is set the hcall should populate the Guest-State-Elements in the requested GSB with the stat counter values. Currently following five counters are supported: * l0_guest_heap_size_inuse * l0_guest_heap_size_max * l0_guest_pagetable_size_inuse * l0_guest_pagetable_size_max * l0_guest_pagetable_reclaimed At the moment '0' is being reported for all these counters as these counters doesn't align with how L0-Qemu manages Guest memory. The patch implements support for these counters by adding new members to the 'struct SpaprMachineStateNested'. These new members are then plugged into the existing 'guest_state_element_types[]' with the help of a new macro 'GSBE_NESTED_MACHINE_DW' together with a new helper 'get_machine_ptr()'. guest_state_request_check() is updated to ensure correctness of the requested GSB and finally h_guest_getset_state() is updated to handle the newly introduced flag 'GUEST_STATE_REQUEST_HOST_WIDE'. This patch is tested with the proposed linux-kernel implementation to expose these stat-counter as perf-events at [2]. [1] https://lore.kernel.org/all/20241222140247.174998-2-vaibhav@linux.ibm.com [2] https://lore.kernel.org/all/20241222140247.174998-1-vaibhav@linux.ibm.com Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20250221155449.530645-1-vaibhav@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc: spapr: Enable 2nd DAWR on Power10 pSeries machineShivaprasad G Bhat3-10/+67
As per the PAPR, bit 0 of byte 64 in pa-features property indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find whether kvm supports 2nd DAWR or not. If it's supported, allow user to set the pa-feature bit in guest DT using cap-dawr1 machine capability. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-ID: <173708681866.1678.11128625982438367069.stgit@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/epapr: Do not swap ePAPR magic valuePhilippe Mathieu-Daudé2-2/+2
The ePAPR magic value in $r6 doesn't need to be byte swapped. See ePAPR-v1.1.pdf chapter 5.4.1 "Boot CPU Initial Register State" and the following mailing-list threads: https://lore.kernel.org/qemu-devel/CAFEAcA_NR4XW5DNL4nq7vnH4XRH5UWbhQCxuLyKqYk6_FCBrAA@mail.gmail.com/ https://lore.kernel.org/qemu-devel/D6F93NM6OW2L.2FDO88L38PABR@gmail.com/ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-7-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() methodPhilippe Mathieu-Daudé1-2/+6
Convert DIRTY_HPTE() macro as hpte_set_dirty() method. sPAPR data structures including the hash page table are big-endian regardless of current CPU endian mode, so use the big-endian LD/ST API to access the hash PTEs. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-6-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() methodPhilippe Mathieu-Daudé1-5/+10
Convert CLEAN_HPTE() macro as hpte_set_clean() method. sPAPR data structures including the hash page table are big-endian regardless of current CPU endian mode, so use the big-endian LD/ST API to access the hash PTEs. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-5-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() methodPhilippe Mathieu-Daudé1-4/+8
Convert HPTE_DIRTY() macro as hpte_is_dirty() method. sPAPR data structures including the hash page table are big-endian regardless of current CPU endian mode, so use the big-endian LD/ST API to access the hash PTEs. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-4-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() methodPhilippe Mathieu-Daudé1-5/+9
Convert HPTE_VALID() macro as hpte_is_valid() method. sPAPR data structures including the hash page table are big-endian regardless of current CPU endian mode, so use the big-endian LD/ST API to access the hash PTEs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-3-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() methodPhilippe Mathieu-Daudé1-16/+22
Convert HPTE() macro as hpte_get_ptr() method. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20241220213103.6314-2-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ppc/spapr: Restrict CONFER hypercall to TCGPhilippe Mathieu-Daudé1-0/+2
KVM handles H_CONFER and does not pass it along to QEMU, so only vhyp (as used by TCG spapr) needs to handle it. [npiggin: Add changelog] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250127102620.39159-2-philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 dayshw/ssi/pnv_spi: Make bus names distinct for each controllers of a socketChalapathi V1-0/+2
Create a spi buses with distinct names on each socket so that responders are attached to correct SPI controllers. Change the bus name to chipX.spi.<busnum> where X = 0..<num_sockets> QOM tree on a 2 socket machine: (qemu) info qom-tree /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi) /chip0.spi.0 (SSI) /xscom-spi[0] (memory-region) /chip[1] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi) /chip1.spi.0 (SSI) /xscom-spi[0] (memory-region) Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Message-ID: <20250303141328.23991-4-chalapathi.v@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/xive2: Support crowd-matching when looking for targetFrederic Barrat2-9/+13
XIVE crowd sizes are encoded into a 2-bit field as follows: 0: 0b00 2: 0b01 4: 0b10 16: 0b11 A crowd size of 8 is not supported. If an END is defined with the 'crowd' bit set, then a target can be running on different blocks. It means that some bits from the block VP are masked when looking for a match. It is similar to groups, but on the block instead of the VP index. Most of the changes are due to passing the extra argument 'crowd' all the way to the function checking for matches. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/xive2: Add undelivered group interrupt to backlogFrederic Barrat1-1/+21
When a group interrupt cannot be delivered, we need to: - increment the backlog counter for the group in the NVG table (if the END is configured to keep a backlog). - start a broadcast operation to set the LSMFB field on matching CPUs which can't take the interrupt now because they're running at too high a priority. [npiggin: squash in fixes from milesg] [milesg: only load the NVP if the END is !ignore] [milesg: always broadcast backlog, not only when there are precluded VPs] Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: Add a default formatted PNOR imageNicholas Piggin1-1/+15
The default PNOR image is erased and not recognised by skiboot, so NVRAM gets disabled. This change adds a tiny pnor file that is a proper FFS image with a formatted NVRAM partition. This is recognised by skiboot and will persist across machine reboots. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: Add a PNOR address and size sanity checksNicholas Piggin1-0/+28
The BMC HIOMAP PNOR access protocol has certain limits on PNOR addresses and sizes. Add some sanity checks for these so we don't get strange behaviour. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: Implement LPC FW address space IDSELNicholas Piggin1-6/+9
LPC FW address space is a 256MB (28-bit) region to one of 16-devices that are selected with the IDSEL register. Implement this by making the ISA FW address space 4GB, and move the 256MB OPB alias within that space according to IDSEL. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: raise no-response errors if an LPC transaction failsNicholas Piggin1-0/+10
If nothing responds to an LPC access, the LPC host controller should set an IRQSTAT error. Model this behaviour. skiboot uses this error to "probe" LPC accesses, among other things to determine if a SuperIO chip is present. After this change it recognizes there is no SuperIO present and does not keep trying to access it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: Support LPC host controller irqs other than serirqsNicholas Piggin1-33/+31
The LPC model has only supported serirqs (ISA device IRQs), however there are internal sources that can raise other interrupts. Update the device to handle these interrupt sources. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/occ: Implement a basic dynamic OCC modelNicholas Piggin1-0/+146
The OCC is an On Chip Controller that handles various thermal and power management. It is a PPC405 microcontroller that runs its own firmware which is out of scope of the powernv machine model. Some dynamic behaviour and interfaces that are important for host CPU testing can be implemented with a much simpler state machine. This change adds a 100ms timer that ticks through a simple state machine that looks for "OCC command requests" coming from host firmware, and responds to them. For now the powercap command is implemented because that is used by OPAL and exported to Linux and is easy to test. $ F=/sys/firmware/opal/powercap/system-powercap/powercap-current $ cat $F 100 $ echo 50 | sudo tee $F 50 $ cat $F 50 Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/occ: Add POWER10 OCC-OPAL data formatNicholas Piggin1-1/+42
Add POWER10 OCC-OPAL data format. POWER10 changes major version and adds a few fields. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/occ: Update pstate frequency tablesNicholas Piggin1-6/+6
OCC pstate frequencies are in kHz, so the OCC data was 3-4MHz. Upgrade to GHz. Make each pstate have a different frequency. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv: Make HOMER memory a RAM regionNicholas Piggin3-239/+487
The HOMER is a region of memory used by host and firmware and microconrollers. It has very little logic by itself, just some BAR registers. Users of this memory should operate on it rather than have HOMER implement them with MMIO registers, which is not the right model. This change switches the implementation of HOMER from MMIO to RAM, and moves the OCC register implementation to in-memory structure accesses performed by the OCC model. This has the downside that access to unimplemented regions of HOMER are no longer flagged. Perhaps that could be done by adding a memory region for HOMER, and ram subregions under that for each implemented part. But for now this takes the simpler approach. Note: This brings some data structure definitions from skiboot, which does not match QEMU coding style but is not changed to make comparisons and updates simpler. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/occ: Better document OCCMISC bitsNicholas Piggin1-5/+9
Use defines for the OCCMISC register bits, and add a comment about the IRQ request bit, which QEMU may not model quite correctly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/homer: class-based base and sizeNicholas Piggin1-13/+33
Put HOMER memory region base and size into the class, to allow more code-reuse between different machines in later changes. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/occ: Fix common area sensor offsetsNicholas Piggin1-18/+15
The commit to fix the OCC common area sensor mappings didn't update the register offsets to match. Before this change, skiboot reports: [ 0.347100086,3] OCC: Chip 0 sensor data invalid Afterward, there is no error and the sensor_groups directory appears under /sys/firmware/opal/. The SLW_IMAGE_BASE address looks like a workaround to intercept firmware memory accesses, but that does not seem to be required now (and would have been broken by the OCC common area region mapping change anyway). So it can be removed. Fixes: 3a1b70b66b5cb4 ("ppc/pnv: Fix OCC common area region mapping") Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/homer: Make dummy reads return 0Nicholas Piggin1-2/+2
HOMER memory implements some dummy registers that return a nonsense value to satisfy skiboot accesses caused by "SLW" init and register save/restore programming that has never worked under QEMU: [ 0.265000943,3] SLW: Failed to set HRMOR for CPU 0,RC=0x1 [ 0.265356988,3] Disabling deep stop states To simplify a later change to implement HOMER as a RAM area, make these return zero, which has the same result. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/homer: Fix OCC registersNicholas Piggin1-12/+29
The HOMER OCC registers seem to have bitrotted and fail for various reasons on powernv8, 9, and 10. The major problems are that POWER8 has the wrong version value and its pstate ordering is incorrect. POWER9/10 have not set the OCC state to active. Non-zero chips are also set to OCC slaves for POWER9/10. Unfortunately skiboot has also bitrotted and requires fixes that are not yet in the bios files to run. With a patched skiboot, before this change, powernv9/10 report: [ 0.262050394,3] OCC: Chip: 0: OCC not active [ 0.262128603,3] OCC: Initialization on all chips did not complete(timed out) powernv8 reports: [ 0.173572100,3] OCC: Unknown OCC-OPAL interface version. [ 0.173812059,3] OCC: Initialization on all chips did not complete(timed out) After this patch, all report: [ 0.176815668,5] OCC: All Chip Rdy after 0 ms Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/pnv/phb4: Add pervasive chiplet support to PHB4/5Nicholas Piggin1-0/+8
Each non-core chiplet on a chip has a "pervasive chiplet" unit and its xscom register set. This adds support for PHB4/5. skiboot reads the CPLT_CONF1 register in __phb4/5_get_max_link_width(), which shows up as unimplemented xscom reads. Set a value in PCI CONF1 register's link-width field to demonstrate skiboot doing something interesting with it. In the bigger picture, it might be better to model the pervasive chiplet type as parent that each non-core chiplet model derives from. For now this is enough to get the PHB registers implemented and working for skiboot, and provides a second example (after the N1 chiplet) that will help if the design is reworked as such. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
4 daysppc/ppc405: Remove boardsCédric Le Goater5-1934/+0
The ref405ep machine is the only PPC 405 machine. Drop all support by removing the SoC and associated devices as-well as the machine. Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-3-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20250204080649.836155-3-clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
7 daysexec: Declare tlb_flush*() in 'exec/cputlb.h'Philippe Mathieu-Daudé1-0/+1
Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20241114011310.3615-19-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11 dayshw/ppc/spapr: Restrict part of PAGE_INIT hypercall to TCGPhilippe Mathieu-Daudé1-1/+3
Restrict the tb_flush() call to TCG. Assert we are using KVM or TCG. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-Id: <20250127102620.39159-3-philmd@linaro.org>
2025-02-24hw: Centralize handling of -machine dumpdtb optionPeter Maydell4-4/+0
Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every board model that has an FDT. It's up to the board code to make sure it calls qemu_fdt_dumpdtb() in the right place. This means we're inconsistent and often just ignore the user's command line argument: * if the board doesn't have an FDT at all * if the board supports FDT, but there happens not to be one present (usually because of a missing -fdt option) This isn't very helpful because it gives the user no clue why their option was ignored. However, in order to support the QMP/HMP dumpdtb commands we require now that every FDT machine stores a pointer to the FDT in MachineState::fdt. This means we can handle -machine dumpdtb centrally by calling the qmp_dumpdtb() function, unifying its handling with the QMP/HMP commands. All the board code calls to qemu_fdt_dumpdtb() can then be removed. For this commit we retain the existing behaviour that if there is no FDT we silently ignore the -machine dumpdtb option. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-22Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi1-3/+17
into staging virtio,pc,pci: features, fixes, cleanups Features: SR-IOV emulation for pci virtio-mem-pci support for s390 interleave support for cxl big endian support for vdpa svq new QAPI events for vhost-user Also vIOMMU reset order fixups are in. Fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAme4b8sPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpHKcIAKPJsVqPdda2dJ7b7FdyRT0Q+uwezXqaGHd4 # 7Lzih1wsxYNkwIAyPtEb76/21qiS7BluqlUCfCB66R9xWjP5/KfvAFj4/r4AEduE # fxAgYzotNpv55zcRbcflMyvQ42WGiZZHC+o5Lp7vDXUP3pIyHrl0Ydh5WmcD+hwS # BjXvda58TirQpPJ7rUL+sSfLih17zQkkDcfv5/AgorDy1wK09RBKwMx/gq7wG8yJ # twy8eBY2CmfmFD7eTM+EKqBD2T0kwLEeLfS/F/tl5Fyg6lAiYgYtCbGLpAmWErsg # XZvfZmwqL7CNzWexGvPFnnLyqwC33WUP0k0kT88Y5wh3/h98blw= # =tej8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 21 Feb 2025 20:21:31 HKT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (41 commits) docs/devel/reset: Document reset expectations for DMA and IOMMU hw/vfio/common: Add a trace point in vfio_reset_handler hw/arm/smmuv3: Move reset to exit phase hw/i386/intel-iommu: Migrate to 3-phase reset hw/virtio/virtio-iommu: Migrate to 3-phase reset vhost-user-snd: correct the calculation of config_size net: vhost-user: add QAPI events to report connection state hw/virtio/virtio-nsm: Respond with correct length vdpa: Fix endian bugs in shadow virtqueue MAINTAINERS: add more files to `vhost` cryptodev/vhost: allocate CryptoDevBackendVhost using g_mem0() vhost-iova-tree: Update documentation vhost-iova-tree, svq: Implement GPA->IOVA & partial IOVA->HVA trees vhost-iova-tree: Implement an IOVA-only tree amd_iommu: Use correct bitmask to set capability BAR amd_iommu: Use correct DTE field for interrupt passthrough hw/virtio: reset virtio balloon stats on machine reset mem/cxl_type3: support 3, 6, 12 and 16 interleave ways hw/mem/cxl_type3: Ensure errp is set on realization failure hw/mem/cxl_type3: Fix special_ops memory leak on msix_init_exclusive_bar() failure ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-20hw/ppc/spapr_pci: Do not reject VFs created after a PFAkihiko Odaki1-1/+3
A PF may automatically create VFs and the PF may be function 0. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Tested-by: Shivaprasad G Bhat <sbhat@linux.ibm.com> Message-Id: <20250116-reuse-v20-2-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-20hw/ppc/spapr_pci: Do not create DT for disabled PCI deviceAkihiko Odaki1-2/+14
Disabled means it is a disabled SR-IOV VF and hidden from the guest. Do not create DT when starting the system and also keep the disabled PCI device not linked to DRC, which generates DT in case of hotplug. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Shivaprasad G Bhat<sbhat@linux.ibm.com> Tested-by: Shivaprasad G Bhat<sbhat@linux.ibm.com> Message-Id: <20250116-reuse-v20-1-7cb370606368@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-02-16hw/timer/xilinx_timer: Make device endianness configurablePhilippe Mathieu-Daudé1-0/+1
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "endianness" property to select the device endianness. This property is unspecified by default, and machines need to set it explicitly. Set the proper endianness for each machine using the device. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250213122217.62654-5-philmd@linaro.org>
2025-02-16hw/intc/xilinx_intc: Make device endianness configurablePhilippe Mathieu-Daudé1-0/+1
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "endianness" property to select the device endianness. This property is unspecified by default, and machines need to set it explicitly. Set the proper endianness for each machine using the device. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250213122217.62654-3-philmd@linaro.org>
2025-02-16hw/boards: Do not create unusable default if=sd drivesPhilippe Mathieu-Daudé13-13/+0
A number of machines create an if=sd drive by default even though they lack an SD bus, and therefore cannot use the drive. This drive is created when the machine sets flag @auto_create_sdcard. See for example running HMP "info block" on the HPPA C3700 machine: $ qemu-system-hppa -M C3700 -monitor stdio -S (qemu) info block floppy0: [not inserted] Removable device: not locked, tray closed sd0: [not inserted] Removable device: not locked, tray closed $ qemu-system-hppa -M C3700 -sd /bin/sh qemu-system-hppa: -sd /bin/sh: machine type does not support if=sd,bus=0,unit=0 Delete that from machines that lack an SD bus. Note, only the ARM and RISCV targets use such feature: $ git grep -wl IF_SD hw | cut -d/ -f-2 | sort -u hw/arm hw/riscv $ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-5-philmd@linaro.org>
2025-02-16hw/boards: Rename no_sdcard -> auto_create_sdcardPhilippe Mathieu-Daudé13-13/+13
Invert the 'no_sdcard' logic, renaming it as the more explicit "auto_create_sdcard". Machines are supposed to create a SD Card drive when this flag is set. In many cases it doesn't make much sense (as boards don't expose SD Card host controller), but this is patch only aims to expose that nonsense; so no logical change intended (mechanical patch using gsed). Most of the changes are: - mc->no_sdcard = ON_OFF_AUTO_OFF; + mc->auto_create_sdcard = true; Except in . hw/core/null-machine.c . hw/arm/xilinx_zynq.c . hw/s390x/s390-virtio-ccw.c where the disabled option is manually removed (since default): - mc->no_sdcard = ON_OFF_AUTO_ON; + mc->auto_create_sdcard = false; - mc->auto_create_sdcard = false; and in system/vl.c we change the 'default_sdcard' type to boolean. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20250204200934.65279-4-philmd@linaro.org>
generated by cgit v1.1 at 2025-03-15 08:27:17 +0000