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2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic4-4/+5
While loading the executable, some platforms (like AVR) need to detect CPU type that executable is built for - and, with this patch, this is enabled by reading the field 'e_flags' of the ELF header of the executable in question. The change expands functionality of the following functions: - load_elf() - load_elf_as() - load_elf_ram() - load_elf_ram_sym() The argument added to these functions is called 'pflags' and is of type 'uint32_t*' (that matches 'pointer to 'elf_word'', 'elf_word' being the type of the field 'e_flags', in both 32-bit and 64-bit variants of ELF header). Callers are allowed to pass NULL as that argument, and in such case no lookup to the field 'e_flags' will happen, and no information will be returned, of course. CC: Richard Henderson <rth@twiddle.net> CC: Peter Maydell <peter.maydell@linaro.org> CC: Edgar E. Iglesias <edgar.iglesias@gmail.com> CC: Michael Walle <michael@walle.cc> CC: Thomas Huth <huth@tuxfamily.org> CC: Laurent Vivier <laurent@vivier.eu> CC: Philippe Mathieu-Daudé <f4bug@amsat.org> CC: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> CC: Aurelien Jarno <aurelien@aurel32.net> CC: Jia Liu <proljc@gmail.com> CC: David Gibson <david@gibson.dropbear.id.au> CC: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> CC: BALATON Zoltan <balaton@eik.bme.hu> CC: Christian Borntraeger <borntraeger@de.ibm.com> CC: Thomas Huth <thuth@redhat.com> CC: Artyom Tarasenko <atar4qemu@gmail.com> CC: Fabien Chouteau <chouteau@adacore.com> CC: KONRAD Frederic <frederic.konrad@adacore.com> CC: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1580079311-20447-24-git-send-email-aleksandar.markovic@rt-rk.com>
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-01-10Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-2/+2
* Compat machines fix (Denis) * Command line parsing fixes (Michal, Peter, Xiaoyao) * Cooperlake CPU model fixes (Xiaoyao) * i386 gdb fix (mkdolata) * IOEventHandler cleanup (Philippe) * icount fix (Pavel) * RR support for random number sources (Pavel) * Kconfig fixes (Philippe) # gpg: Signature made Wed 08 Jan 2020 10:41:00 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (38 commits) chardev: Use QEMUChrEvent enum in IOEventHandler typedef chardev: use QEMUChrEvent instead of int chardev/char: Explicit we ignore some QEMUChrEvent in IOEventHandler monitor/hmp: Explicit we ignore a QEMUChrEvent in IOEventHandler monitor/qmp: Explicit we ignore few QEMUChrEvent in IOEventHandler virtio-console: Explicit we ignore some QEMUChrEvent in IOEventHandler vhost-user-blk: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-net: Explicit we ignore few QEMUChrEvent in IOEventHandler vhost-user-crypto: Explicit we ignore some QEMUChrEvent in IOEventHandler ccid-card-passthru: Explicit we ignore QEMUChrEvent in IOEventHandler hw/usb/redirect: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/usb/dev-serial: Explicit we ignore few QEMUChrEvent in IOEventHandler hw/char/terminal3270: Explicit ignored QEMUChrEvent in IOEventHandler hw/ipmi: Explicit we ignore some QEMUChrEvent in IOEventHandler hw/ipmi: Remove unnecessary declarations target/i386: Add missed features to Cooperlake CPU model target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub hw/rtc/mc146818: Add missing dependency on ISA Bus hw/nvram/Kconfig: Restrict CHRP NVRAM to machines using OpenBIOS or SLOF ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-01-08chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé2-2/+2
The Chardev events are listed in the QEMUChrEvent enum. By using the enum in the IOEventHandler typedef we: - make the IOEventHandler type more explicit (this handler process out-of-band information, while the IOReadHandler is in-band), - help static code analyzers. This patch was produced with the following spatch script: @match@ expression backend, opaque, context, set_open; identifier fd_can_read, fd_read, fd_event, be_change; @@ qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event, be_change, opaque, context, set_open); @depends on match@ identifier opaque, event; identifier match.fd_event; @@ static -void fd_event(void *opaque, int event) +void fd_event(void *opaque, QEMUChrEvent event) { ... } Then the typedef was modified manually in include/chardev/char-fe.h. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Corey Minyard <cminyard@mvista.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20191218172009.8868-15-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-01-07mips/cps: fix setting saar propertyMarc-André Lureau1-1/+1
There is no "saar" property. Note: I haven't been able to test this code. Help welcome. May fix commit 043715d1e0fbb3e3411be3f898c5b77b7f90327a ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2020-01-07dp8393x: replace PROP_PTR with PROP_LINKMarc-André Lureau1-1/+2
Link property is the correct way to pass a MemoryRegion to a device for DMA purposes. Sidenote: as a sysbus device, this remains non-usercreatable even though we can drop the specific flag here. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Laurent Vivier <laurent@vivier.eu>
2020-01-07mips: use sysbus_mmio_get_region() instead of internal fieldsMarc-André Lureau1-1/+2
Register the memory region with sysbus_init_mmio() and look it up with sysbus_mmio_get_region() to avoid accessing internal device fields. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-01-07mips: use sysbus_add_io()Marc-André Lureau1-2/+1
sysbus devices should use the associated helper function instead of calling memory_region_add_subregion() manually. This simplifies slightly the code. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-01-07mips: baudbase is 115200 by defaultMarc-André Lureau1-1/+0
(The default value is set for TYPE_SERIAL in serial_properties) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2020-01-07mips: inline serial_init()Marc-André Lureau1-3/+12
The function is specific to mipssim, let's inline it. (when inlining, we use a DeviceState variable instead of SerialIO, as it is the most common type used, and avoids having too many casts) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2020-01-07serial: start making SerialMM a sysbus deviceMarc-André Lureau2-2/+2
Memory mapped serial device is in fact a sysbus device. The following patches will make use of sysbus facilities for resource and registration. In particular, "serial-mm: use sysbus facilities" will move internal serial realization to serial_mm_realize callback to follow qdev best practices. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17hw: replace hw/i386/pc.h with a header just for the i8259Paolo Bonzini4-4/+4
Remove the need to include i386/pc.h to get to the i8259 functions. This is enough to remove the inclusion of hw/i386/pc.h from all non-x86 files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-16hw/mips: Deprecate the r4k machinePhilippe Mathieu-Daudé1-0/+1
The r4k machine was introduced in 2005 (6af0bf9c7) and its last logical change was in 2005 (9542611a6). After that, one can count 164 maintenance commits (QEMU API changes) with the exception of 1 fix in 2015 (memory leak, commit 3ad9fd5a). This machine was introduced as a proof of concept to run a MIPS CPU. Two years later, the Malta machine was added (commit 5856de80), modeling a real platform. Note also this machine has no specification except 5 lines in the header of this file: * emulates a simple machine with ISA-like bus. * ISA IO space mapped to the 0x14000000 (PHYS) and * ISA memory at the 0x10000000 (PHYS, 16Mb in size). * All peripherial devices are attached to this "bus" with * the standard PC ISA addresses. The Linux kernel support for this machine has been dropped more than 10 years ago in commit 302922e5. It is time to deprecate this obsolete machine. Users are recommended to use the Malta board, and its hardware is well documented. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Message-Id: <20191125104103.28962-1-philmd@redhat.com>
2019-12-16mips: r4000: Renovate coding styleFilip Bozuta1-21/+34
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in file: hw/mips/mips_r4k.c This mips r4000 machine file was edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-5-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: malta: Renovate coding styleFilip Bozuta1-85/+87
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_malta.c hw/mips/gt64xxx_pci.c tests/acceptance/linux_ssh_mips_malta.py All these mips malta machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-3-git-send-email-Filip.Bozuta@rt-rk.com>
2019-12-16mips: jazz: Renovate coding styleFilip Bozuta1-13/+19
The script checkpatch.pl located in scripts folder was used to detect all errors and warrnings in files: hw/mips/mips_jazz.c hw/display/jazz_led.c hw/dma/rc4030.c All these mips jazz machine files were edited and all the errors and warrings generated by the checkpatch.pl script were corrected and then the script was ran again to make sure there are no more errors and warnings. Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1575640687-20744-2-git-send-email-Filip.Bozuta@rt-rk.com>
2019-11-19hw/mips/gt64xxx: Remove dynamic field width from trace eventsPhilippe Mathieu-Daudé2-10/+10
Since not all trace backends support dynamic field width in format (dtrace via stap does not), replace by a static field width instead. We previously passed to the trace API 'width << 1' as the number of hex characters to display (the dynamic field width). We don't need this anymore. Instead, display the size of bytes accessed. Fixes: ab6bff424f ("gt64xxx_pci: Convert debug printf to trace events") Reported-by: Eric Blake <eblake@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Buglink: https://bugs.launchpad.net/qemu/+bug/1844817 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05hw/pci-host/piix: Define and use the PIIX IRQ Route Control RegistersPhilippe Mathieu-Daudé1-2/+2
The IRQ Route Control registers definitions belong to the PIIX chipset. We were only defining the 'A' register. Define the other B, C and D registers, and use them. Acked-by: Paul Durrant <paul@xen.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05hw/isa/piix4: Move piix4_create() to hw/isa/piix4.cPhilippe Mathieu-Daudé2-28/+1
Now that we properly refactored the piix4_create() function, let's move it to hw/isa/piix4.c where it belongs, so it can be reused on other places. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()Philippe Mathieu-Daudé1-18/+29
The Malta board instantiate a PIIX4 chipset doing various calls. Refactor all those related calls into a single function: piix4_create(). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05hw/mips/mips_malta: Create IDE hard drive array dynamicallyPhilippe Mathieu-Daudé1-2/+5
In the next commit we'll refactor the PIIX4 code out of mips_malta_init(). As a preliminary step, add the 'ide_drives' variable and create the drive array dynamically. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05piix4: Add a MC146818 RTC Controller as specified in datasheetPhilippe Mathieu-Daudé1-3/+1
Remove mc146818rtc instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-13-hpoussin@reactos.org> [PMD: rebased, set RTC base_year to 2000] Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05piix4: Add an i8254 PIT Controller as specified in datasheetHervé Poussineau1-4/+0
Remove i8254 instanciated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-10-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05piix4: Add an i8257 DMA Controller as specified in datasheetHervé Poussineau1-2/+0
The i8257 is not a chipset on the Malta board, but is part of the PIIX4 chipset. Create the i8257 in the PIIX4 code, remove the one instantiated in malta board, to not have it twice. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Esteban Bosse <estebanbosse@gmail.com> [PMD: rebased, reworded description] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05piix4: Rename PIIX4 object to piix4-isaHervé Poussineau1-1/+1
Other piix4 parts are already named piix4-ide and piix4-usb-uhci. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Esteban Bosse <estebanbosse@gmail.com> [PMD: rebased] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-11-05piix4: Add an i8259 Interrupt Controller as specified in datasheetHervé Poussineau1-19/+13
Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out. Remove i8259 instanciated in malta board, to not have it twice. We can also remove the now unused piix4_init() function. Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-10-24hw: Move MC146818 device from hw/timer/ to hw/rtc/ subdirectoryPhilippe Mathieu-Daudé4-4/+4
The MC146818 is a Real Time Clock, not a timer. Move it under the hw/rtc/ subdirectory. Use copyright statement from 80cabfad163 for "hw/rtc/mc146818rtc.h". Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191003230404.19384-4-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-10-04mips: fix memory leaks in board initializationPaolo Bonzini2-0/+3
They are not a big deal, but they upset asan. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2019-10-04hw/isa: Introduce a CONFIG_ISA_SUPERIO switch for isa-superio.cThomas Huth1-0/+1
Currently, isa-superio.c is always compiled as soon as CONFIG_ISA_BUS is enabled. But there are also machines that have an ISA BUS without any of the superio chips attached to it, so we should not compile isa-superio.c in case we only compile a QEMU for such a machine. Thus add a proper CONFIG_ISA_SUPERIO switch so that this file only gets compiled when we really, really need it. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-12hw/mips/mips_jazz: Remove no-longer-necessary override of do_unassigned_accessPeter Maydell1-23/+4
Now that the MIPS CPU implementation uses the new do_transaction_failed hook, we can remove the old code that handled the do_unassigned_access hook. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20190802160458.25681-4-peter.maydell@linaro.org>
2019-09-12hw/mips/mips_jazz: Override do_transaction_failed hookPeter Maydell1-8/+46
The MIPS Jazz ('magnum' and 'pica61') boards have some code which overrides the CPU's do_unassigned_access hook, so they can intercept it and not raise exceptions on data accesses to invalid addresses, only for instruction fetches. We want to switch MIPS over to using the do_transaction_failed hook instead, so add an intercept for that as well, and make the board code install whichever hook the CPU is actually using. Once we've changed the CPU implementation we can remove the redundant code for the old hook. Note: I am suspicious that the behaviour as implemented here may not be what the hardware really does. It was added in commit 54e755588cf1e90f0b14 to restore the behaviour that was broken by commit c658b94f6e8c206c59d. But prior to commit c658b94f6e8c206c59d every MIPS board generated exceptions for instruction access to invalid addresses but not for data accesses; and other boards, notably Malta, were fixed by making all invalid accesses behave as reads-as-zero (see the call to empty_slot_init() in mips_malta_init()). Hardware that raises exceptions for instruction access and not data access seems to me to be an unlikely design, and it's possible that the right way to emulate this is to make the Jazz boards do what we did with Malta (or some variation of that). Nonetheless, since I don't have access to real hardware to test against I have taken the approach of "make QEMU continue to behave the same way it did before this commit". I have updated the comment to correct the parts that are no longer accurate and note that the hardware might behave differently. The test case for the need for the hook-hijacking is in https://bugs.launchpad.net/qemu/+bug/1245924 That BIOS will boot OK either with this overriding of both hooks, or with a simple "global memory region to ignore bad accesses of all types", so it doesn't provide evidence either way, unfortunately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Hervé Poussineau <hpoussin@reactos.org> Message-Id: <20190802160458.25681-2-peter.maydell@linaro.org>
2019-08-19target/mips: Style improvements in mips_mipssim.cAleksandar Markovic1-7/+12
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-17-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19target/mips: Style improvements in mips_malta.cAleksandar Markovic1-88/+128
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-16-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19target/mips: Style improvements in mips_int.cAleksandar Markovic1-1/+2
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19target/mips: Style improvements in mips_fulong2e.cAleksandar Markovic1-38/+58
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-14-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19target/mips: Style improvements in cps.cAleksandar Markovic1-2/+4
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1566216496-17375-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-16sysemu: Split sysemu/runstate.h off sysemu/sysemu.hMarkus Armbruster3-0/+3
sysemu/sysemu.h is a rather unfocused dumping ground for stuff related to the system-emulator. Evidence: * It's included widely: in my "build everything" tree, changing sysemu/sysemu.h still triggers a recompile of some 1100 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h, down from 5400 due to the previous two commits). * It pulls in more than a dozen additional headers. Split stuff related to run state management into its own header sysemu/runstate.h. Touching sysemu/sysemu.h now recompiles some 850 objects. qemu/uuid.h also drops from 1100 to 850, and qapi/qapi-types-run-state.h from 4400 to 4200. Touching new sysemu/runstate.h recompiles some 500 objects. Since I'm touching MAINTAINERS to add sysemu/runstate.h anyway, also add qemu/main-loop.h. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190812052359.30071-30-armbru@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [Unbreak OS-X build]
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster2-0/+2
In my "build everything" tree, changing hw/qdev-properties.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). Many places including hw/qdev-properties.h (directly or via hw/qdev.h) actually need only hw/qdev-core.h. Include hw/qdev-core.h there instead. hw/qdev.h is actually pointless: all it does is include hw/qdev-core.h and hw/qdev-properties.h, which in turn includes hw/qdev-core.h. Replace the remaining uses of hw/qdev.h by hw/qdev-properties.h. While there, delete a few superfluous inclusions of hw/qdev-core.h. Touching hw/qdev-properties.h now recompiles some 1200 objects. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrangé" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190812052359.30071-22-armbru@redhat.com>
2019-08-16Include hw/hw.h exactly where neededMarkus Armbruster9-9/+0
In my "build everything" tree, changing hw/hw.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The previous commits have left only the declaration of hw_error() in hw/hw.h. This permits dropping most of its inclusions. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-19-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
In my "build everything" tree, changing migration/vmstate.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). hw/hw.h supposedly includes it for convenience. Several other headers include it just to get VMStateDescription. The previous commit made that unnecessary. Include migration/vmstate.h only where it's still needed. Touching it now recompiles only some 1600 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-16-armbru@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster3-0/+3
In my "build everything" tree, changing hw/irq.h triggers a recompile of some 5400 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). hw/hw.h supposedly includes it for convenience. Several other headers include it just to get qemu_irq and.or qemu_irq_handler. Move the qemu_irq and qemu_irq_handler typedefs from hw/irq.h to qemu/typedefs.h, and then include hw/irq.h only where it's still needed. Touching it now recompiles only some 500 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-13-armbru@redhat.com>
2019-08-16Include sysemu/reset.h a lot lessMarkus Armbruster6-0/+8
In my "build everything" tree, changing sysemu/reset.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The main culprit is hw/hw.h, which supposedly includes it for convenience. Include sysemu/reset.h only where it's needed. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-9-armbru@redhat.com>
2019-07-05hw: Replace global smp variables with MachineState for all remaining archsLike Xu2-1/+3
The global smp variables in alpha/hppa/mips/openrisc/sparc*/xtensa codes are replaced with smp properties from MachineState. A local variable of the same name would be introduced in the declaration phase if it's used widely in the context OR replace it on the spot if it's only used once. No semantic changes. Signed-off-by: Like Xu <like.xu@linux.intel.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190518205428.90532-10-like.xu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-05machine: Refactor smp-related call chains to pass MachineStateLike Xu1-11/+11
To get rid of the global smp_* variables we're currently using, it's recommended to pass MachineState in the list of incoming parameters for functions that use global smp variables, thus some redundant parameters are dropped. It's applied for legacy smbios_*(), *_machine_reset(), hot_add_cpu() and mips *_create_cpu(). Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Like Xu <like.xu@linux.intel.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190518205428.90532-3-like.xu@linux.intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-07-02hw/mips: Express dependencies of the r4k platform with KconfigPhilippe Mathieu-Daudé1-0/+10
This platform use standard PC devices connected to an ISA bus. Networking is provided by a ne2000 chipset. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-5-philmd@redhat.com>
2019-07-02hw/mips: Express dependencies of the Jazz machine with KconfigPhilippe Mathieu-Daudé1-0/+17
The Jazz use the RC4030 Asic to provide an EISA bus and DMA/IRQ. The framebuffer display is managed by a G364, the network card is a Sonic DP83932. A QLogic ESP216 provides a SCSI bus. None, for the both machine variants (PICA-61 and Magnum 4000), the DP83932 chipset is soldered on the board, and is MMIO-mapped (selected via Chip Select). Therefore we have to enforce the 'select' Kconfig rule (we can not use the 'imply' rule helpful when devices are connected on a bus). Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-4-philmd@redhat.com>
2019-07-02hw/mips: Express dependencies of the MIPSsim machine with KconfigPhilippe Mathieu-Daudé1-0/+3
The MIPSsim machine only emulates an 8250 UART and a simple network controller, connected via an ISA bus. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190701112612.14758-3-philmd@redhat.com>
2019-06-26hw/mips/gt64xxx_pci: Align the pci0-mem sizePhilippe Mathieu-Daudé1-1/+2
One byte is missing, use an aligned size. (qemu) info mtree memory-region: pci0-mem 0000000000000000-00000000fffffffe (prio 0, i/o): pci0-mem ^ Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-8-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Convert debug printf()s to trace eventsPhilippe Mathieu-Daudé2-19/+14
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-7-f4bug@amsat.org>
2019-06-26hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug printf()Philippe Mathieu-Daudé1-11/+37
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190624222844.26584-6-f4bug@amsat.org>
generated by cgit v1.1 at 2024-07-22 16:23:05 +0000