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| author | Philippe Mathieu-Daudé <philmd@redhat.com> | 2019-10-15 14:05:42 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@redhat.com> | 2019-11-05 23:33:12 +0100 |
| commit | 4b19de14b145ac1df3082f625e3b8f9dcb0e1918 (patch) | |
| tree | 5d689de0bc7383e0b03da4b0bd5d04c7921a12d0 /hw/mips | |
| parent | 0063454affb3c5a595539a3cad9e20e7229d8fac (diff) | |
| download | qemu-4b19de14b145ac1df3082f625e3b8f9dcb0e1918.zip qemu-4b19de14b145ac1df3082f625e3b8f9dcb0e1918.tar.gz qemu-4b19de14b145ac1df3082f625e3b8f9dcb0e1918.tar.bz2 | |
hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.
Acked-by: Paul Durrant <paul@xen.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Diffstat (limited to 'hw/mips')
| -rw-r--r-- | hw/mips/gt64xxx_pci.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c277398..5cab9c1 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ - pic_irq = piix4_dev->config[0x60 + irq_num]; + pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to it. */ pic_level = 0; for (i = 0; i < 4; i++) { - if (pic_irq == piix4_dev->config[0x60 + i]) { + if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |= pci_irq_levels[i]; } } |