aboutsummaryrefslogtreecommitdiff
path: root/hw/intc
AgeCommit message (Expand)AuthorFilesLines
2023-06-19hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1Peter Maydell1-1/+1
2023-06-16hw/intc: Set physical cpuid route for LoongArch ipi deviceTianrui Zhao1-7/+37
2023-06-14hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.Tommy Wu1-2/+2
2023-06-10pnv/xive2: Quiet down some error messagesFrederic Barrat1-0/+4
2023-06-10pnv/xive2: Handle TIMA access through all portsFrederic Barrat2-1/+5
2023-06-10pnv/xive2: Introduce macros to manipulate TIMA addressesFrederic Barrat1-7/+7
2023-06-10pnv/xive2: Allow writes to the Physical Thread Enable registersFrederic Barrat1-0/+1
2023-06-10pnv/xive2: Add definition for the ESB cache configuration registerFrederic Barrat2-0/+11
2023-06-10pnv/xive2: Add definition for TCTXT Config registerFrederic Barrat2-1/+11
2023-06-06Merge tag 'pull-request-2023-06-06' of https://gitlab.com/thuth/qemu into sta...Richard Henderson1-3/+3
2023-06-05bulk: Remove pointless QOM castsPhilippe Mathieu-Daudé1-3/+3
2023-06-05hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxesJiaxun Yang1-3/+3
2023-05-15hw/intc: Add NULL pointer check on LoongArch ipi deviceSong Gao2-11/+30
2023-05-15hw/loongarch/virt: Set max 256 cpus support on loongarch virt machineSong Gao1-2/+2
2023-05-15hw/loongarch/virt: Modify ipi as percpu deviceSong Gao1-28/+16
2023-05-15loongarch: mark loongarch_ipi_iocsr re-entrnacy safeAlexander Bulekov1-0/+4
2023-05-06hw/intc: don't use target_ulong for LoongArch ipiAlex Bennée1-1/+1
2023-05-05hw/intc/riscv_aplic: Zero init APLIC internal stateIvan Klokov1-1/+1
2023-05-02hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()Peter Maydell1-5/+2
2023-04-28apic: disable reentrancy detection for apic-msiAlexander Bulekov1-0/+7
2023-03-22*: Add missing includes of qemu/error-report.hRichard Henderson1-0/+1
2023-03-15hw/intc/ioapic: Update KVM routes before redelivering IRQ, on RTE updateDavid Woodhouse1-2/+1
2023-03-08hw/intc/i8259: Implement legacy LTIM Edge/Level Bank SelectDavid Woodhouse2-7/+27
2023-03-08hw/mips: Declare all length properties as unsignedPhilippe Mathieu-Daudé1-2/+2
2023-03-05hw: intc: Use cpu_by_arch_id to fetch CPU stateMayuresh Chitale3-13/+13
2023-02-27hw/intc/i8259: Document i8259_init()Philippe Mathieu-Daudé1-2/+2
2023-02-27hw: Move ioapic*.h to intc/Bernhard Beschow4-5/+123
2023-02-27hw/intc/armv7m_nvic: Use QOM cast CPU() macroPhilippe Mathieu-Daudé1-3/+3
2023-02-27target/arm: Wrap arm_rebuild_hflags calls with tcg_enabledFabiano Rosas1-7/+13
2023-02-16target/arm: Store CPUARMState::nvic as NVICState*Philippe Mathieu-Daudé1-25/+13
2023-02-03target/arm: Mark up sysregs for HFGRTR bits 36..63Peter Maydell1-0/+2
2023-02-03hvf: arm: Add support for GICv3Alexander Graf1-1/+15
2023-01-20Merge tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru into st...Peter Maydell2-0/+2
2023-01-20include/hw/ppc: Split pnv_chip.h off pnv.hMarkus Armbruster2-0/+2
2023-01-19Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent...Peter Maydell1-6/+6
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé4-20/+20
2023-01-16hw/intc: Mark more interrupt-controller files as target independentThomas Huth1-4/+4
2023-01-16hw/intc: Move some files out of the target-specific source setPhilippe Mathieu-Daudé1-2/+2
2023-01-16Merge tag 'mips-20230113' of https://github.com/philmd/qemu into stagingPeter Maydell6-40/+68
2023-01-13hw/intc: Extract the IRQ counting functions into a separate fileThomas Huth5-33/+64
2023-01-13hw/intc/i8259: Make using the isa_pic singleton more type-safeBernhard Beschow1-7/+4
2023-01-12hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'Philippe Mathieu-Daudé1-15/+13
2023-01-12hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type namePhilippe Mathieu-Daudé1-19/+19
2023-01-12hw/arm/omap: Drop useless casts from void * to pointerPhilippe Mathieu-Daudé1-6/+6
2023-01-07Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into s...Peter Maydell2-7/+57
2023-01-06hw/intc/loongarch_pch: Change default irq number of pch irq controllerTianrui Zhao1-1/+2
2023-01-06hw/intc/loongarch_pch_pic: add irq number propertyTianrui Zhao1-4/+30
2023-01-06hw/intc/loongarch_pch_msi: add irq number propertyTianrui Zhao1-3/+26
2023-01-06hw/intc: sifive_plic: Fix the pending register range checkBin Meng1-2/+3
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng1-2/+3
generated by cgit v1.1 at 2024-12-29 08:36:09 +0000