diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-05-21 11:23:04 +0100 |
|---|---|---|
| committer | Song Gao <gaosong@loongson.cn> | 2023-06-05 11:08:55 +0800 |
| commit | 8555ddc671203969b0e6eb651e538d02a9a79b3a (patch) | |
| tree | 6f76e13a63ebba8c2164493e2fcddd171b85a362 /hw/intc | |
| parent | 848a6caa88b9f082c89c9b41afa975761262981d (diff) | |
| download | qemu-8555ddc671203969b0e6eb651e538d02a9a79b3a.zip qemu-8555ddc671203969b0e6eb651e538d02a9a79b3a.tar.gz qemu-8555ddc671203969b0e6eb651e538d02a9a79b3a.tar.bz2 | |
hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes
As per "Loongson 3A5000/3B5000 Processor Reference Manual",
Loongson 3A5000's IPI implementation have 4 mailboxes per
core.
However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as
percpu device"), the number of IPI mailboxes was reduced to
one, which mismatches actual hardware.
It won't affect LoongArch based system as LoongArch boot code
only uses the first mailbox, however MIPS based Loongson boot
code uses all 4 mailboxes.
Fixes Coverity CID: 1512452, 1512453
Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/loongarch_ipi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index d6ab917..3e45381 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -238,14 +238,14 @@ static void loongarch_ipi_init(Object *obj) static const VMStateDescription vmstate_ipi_core = { .name = "ipi-single", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(status, IPICore), VMSTATE_UINT32(en, IPICore), VMSTATE_UINT32(set, IPICore), VMSTATE_UINT32(clear, IPICore), - VMSTATE_UINT32_ARRAY(buf, IPICore, 2), + VMSTATE_UINT32_ARRAY(buf, IPICore, IPI_MBX_NUM * 2), VMSTATE_END_OF_LIST() } }; |