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2024-05-30hw/intc/arm_gic: Fix writes to GICD_ITARGETSRnSebastian Huber1-0/+7
2024-05-30hw/intc/arm_gic: Fix set pending of PPIsSebastian Huber1-1/+4
2024-05-28hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>Andrey Shumilin1-2/+2
2024-05-17hw/intc/s390_flic: Fix crash that occurs when saving the machine stateThomas Huth1-1/+1
2024-05-10i386: select correct components for no-board buildPaolo Bonzini2-1/+30
2024-05-10s390_flic: add migration-enabled propertyPaolo Bonzini1-1/+5
2024-05-09hw/intc/loongson_ipi: Implement IOCSR address space for MIPSJiaxun Yang1-9/+30
2024-05-09hw/intc/loongarch_ipi: Rename as loongson_ipiJiaxun Yang4-5/+352
2024-05-09hw/intc/loongarch_ipi: Remove pointless MAX_CPU checkJiaxun Yang2-19/+2
2024-05-03kvm: move target-dependent interrupt routing out of kvm-all.cPaolo Bonzini1-0/+28
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell8-12/+12
2024-04-25hw/intc/arm_gicv3: Report the VINMI interruptJinjie Ruan1-2/+12
2024-04-25hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()Jinjie Ruan1-0/+4
2024-04-25hw/intc/arm_gicv3: Implement NMI interrupt priorityJinjie Ruan3-9/+64
2024-04-25hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()Peter Maydell3-12/+98
2024-04-25hw/intc/arm_gicv3: Add NMI handling CPU interface registersPeter Maydell3-5/+148
2024-04-25hw/intc/arm_gicv3: Implement GICD_INMIRJinjie Ruan2-0/+36
2024-04-25hw/intc/arm_gicv3_redist: Implement GICR_INMIR0Jinjie Ruan2-0/+20
2024-04-25hw/intc/arm_gicv3: Add irq non-maskable propertyJinjie Ruan1-0/+38
2024-04-25hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3Jinjie Ruan1-0/+5
2024-04-25hw/intc/arm_gicv3: Add has-nmi property to GICv3 deviceJinjie Ruan3-0/+4
2024-04-25hw/intc/arm_gicv3: Add external IRQ lines for NMIJinjie Ruan1-0/+6
2024-04-24target/nios2: Remove the deprecated Nios II targetPhilippe Mathieu-Daudé3-317/+0
2024-04-02hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabledPeter Maydell1-2/+2
2024-03-22hw/intc: Update APLIC IDC after claiming iforce registerFrank Chang1-0/+1
2024-03-20hw/intc/loongarch_extioi: Fix interrupt routing updateBibo Mao1-1/+1
2024-03-12hw/intc: Check @errp to handle the error of IOAPICCommonClass.realize()Zhao Liu1-0/+4
2024-03-09hw/intc/grlib_irqmp: abort realize when ncpus value is out of rangeClément Chigot1-0/+1
2024-03-09hw/intc/apic: fix memory leakPaolo Bonzini1-4/+2
2024-03-08hw/intc/riscv_aplic: Fix in_clrip[x] read emulationAnup Patel1-2/+15
2024-03-08hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-modeAnup Patel1-4/+16
2024-03-01hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"Thomas Huth1-6/+6
2024-02-15hw/intc/grlib_irqmp: implements multicore irqClément Chigot1-21/+20
2024-02-15hw/intc/grlib_irqmp: implements the multiprocessor status registerClément Chigot1-3/+32
2024-02-15hw/intc/grlib_irqmp: add ncpus propertyClément Chigot1-9/+21
2024-02-15hw/sparc/grlib: split out the headers for each peripheralsClément Chigot1-2/+4
2024-02-14Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ...Peter Maydell3-108/+402
2024-02-14hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabledBernhard Beschow1-0/+13
2024-02-14apic, i386/tcg: add x2apic transitionsBui Quang Minh2-8/+67
2024-02-14apic: add support for x2APIC modeBui Quang Minh2-68/+228
2024-02-14i386/tcg: implement x2APIC registers MSR accessBui Quang Minh2-32/+94
2024-02-13hw/intc/s390_flic: Consolidate the use of device_class_set_parent_realize()Zhao Liu1-2/+3
2024-01-30hw/intc/xics: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
2024-01-11Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into s...Peter Maydell2-154/+267
2024-01-11hw/intc/loongarch_extioi: Add vmstate post_load supportBibo Mao1-44/+76
2024-01-11hw/intc/loongarch_extioi: Add dynamic cpu number supportBibo Mao1-36/+71
2024-01-11hw/loongarch/virt: Set iocsr address space per-board rather than percpuBibo Mao2-18/+46
2024-01-11hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi opsBibo Mao1-59/+77
2024-01-09hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registersPeter Maydell1-0/+11
2024-01-09hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registersPeter Maydell1-4/+13
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