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author | Peter Maydell <peter.maydell@linaro.org> | 2024-03-28 15:33:33 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2024-04-02 10:02:44 +0100 |
commit | 44e25fbc1900c99c91a44e532c5bd680bc403459 (patch) | |
tree | 4490136e721aebc4d98cf5f79fe9222c2a3d295f /hw/intc | |
parent | aaaae12055064ed10c12d8660246f1b4aa06e5ed (diff) | |
download | qemu-44e25fbc1900c99c91a44e532c5bd680bc403459.zip qemu-44e25fbc1900c99c91a44e532c5bd680bc403459.tar.gz qemu-44e25fbc1900c99c91a44e532c5bd680bc403459.tar.bz2 |
hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
If the group of the highest priority pending interrupt is disabled
via ICC_IGRPEN*, the ICC_HPPIR* registers should return
INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture
specification pseudocode functions ICC_HPPIR1_EL1[] and
HighestPriorityPendingInterrupt().)
Make HPPIR reads honour the group disable, the way we already do
when determining whether to preempt in icc_hppi_can_preempt().
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
-rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8..67d8fd0 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1067,7 +1067,7 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } @@ -1104,7 +1104,7 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) */ bool irq_is_secure; - if (cs->hppi.prio == 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } |