index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
disas
/
riscv.c
Age
Commit message (
Expand
)
Author
Files
Lines
2024-01-10
disas/riscv: Add amocas.[w,d,q] instructions
Rob Bradford
1
-0
/
+9
2023-11-07
disas/riscv: Replace TABs with space
Max Chou
1
-3
/
+3
2023-11-07
disas/riscv: Add support for vector crypto extensions
Max Chou
1
-0
/
+137
2023-11-07
disas/riscv: Add rv_codec_vror_vi for vror.vi
Max Chou
1
-1
/
+13
2023-10-12
disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14
Alvin Chang
1
-2
/
+2
2023-07-19
riscv/disas: Fix disas output of upper immediates
Christoph Müllner
1
-3
/
+16
2023-07-10
riscv: Add support for the Zfa extension
Christoph Müllner
1
-0
/
+139
2023-07-10
target/riscv: Add disas support for BF16 extensions
Weiwei Li
1
-0
/
+44
2023-07-10
disas/riscv: Add support for XThead* instructions
Christoph Müllner
1
-0
/
+69
2023-07-10
disas/riscv: Add support for XVentanaCondOps
Christoph Müllner
1
-0
/
+4
2023-07-10
disas/riscv: Provide infrastructure for vendor extensions
Christoph Müllner
1
-2
/
+26
2023-07-10
disas/riscv: Encapsulate opcode_data into decode
Christoph Müllner
1
-1
/
+8
2023-07-10
disas/riscv: Make rv_op_illegal a shared enum value
Christoph Müllner
1
-1
/
+1
2023-07-10
disas/riscv: Move types/constants to new header file
Christoph Müllner
1
-269
/
+1
2023-06-13
disas/riscv.c: Remove redundant parentheses
Weiwei Li
1
-109
/
+110
2023-06-13
disas/riscv.c: Fix lines with over 80 characters
Weiwei Li
1
-61
/
+140
2023-06-13
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
Weiwei Li
1
-370
/
+370
2023-06-13
disas/riscv.c: Support disas for Z*inx extensions
Weiwei Li
1
-4
/
+12
2023-06-13
disas/riscv.c: Support disas for Zcm* extensions
Weiwei Li
1
-1
/
+7
2023-06-13
target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
Weiwei Li
1
-3
/
+7
2023-05-25
disas/riscv: Decode czero.{eqz,nez}
Richard Henderson
1
-0
/
+6
2023-05-05
disas/riscv.c: add disasm support for Zc*
Weiwei Li
1
-1
/
+227
2023-03-14
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
Mikhail Tyutin
1
-9
/
+10
2023-03-14
disas/riscv: Fix slli_uw decoding
Ivan Klokov
1
-4
/
+4
2023-03-05
disas/riscv Fix ctzw disassemble
Ivan Klokov
1
-1
/
+1
2023-02-07
target/riscv: update disas.c for xnor/orn/andn and slli.uw
Philipp Tomsich
1
-4
/
+4
2022-10-14
disas/riscv.c: rvv: Add disas support for vector instructions
Yang Liu
1
-2
/
+1430
2022-09-27
target/riscv: Remove sideleg and sedeleg
Rahul Pathak
1
-2
/
+0
2022-09-07
target/riscv: fix shifts shamt value for rv128c
Frédéric Pétrot
1
-6
/
+21
2022-04-29
disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
Weiwei Li
1
-1
/
+172
2022-01-08
target/riscv: setup everything for rv64 to support rv128 execution
Frédéric Pétrot
1
-0
/
+5
2021-10-07
disas/riscv: Add Zb[abcs] instructions
Philipp Tomsich
1
-3
/
+154
2019-06-27
disas/riscv: Fix `rdinstreth` constraint
Wladimir J. van der Laan
1
-2
/
+3
2019-06-27
disas/riscv: Disassemble reserved compressed encodings as illegal
Michael Clark
1
-17
/
+45
2019-04-18
disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h
Markus Armbruster
1
-1
/
+1
2019-03-19
RISC-V: Remove unnecessary disassembler constraints
Michael Clark
1
-138
/
+0
2018-05-06
RISC-V: Fix missing break statement in disassembler
Michael Clark
1
-1
/
+2
2018-05-06
RISC-V: Include instruction hex in disassembly
Michael Clark
1
-19
/
+20
2018-03-28
RISC-V: Fix incorrect disassembly for addiw
Michael Clark
1
-1
/
+1
2018-03-07
RISC-V Disassembler
Michael Clark
1
-0
/
+3048