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| author | Ivan Klokov <ivan.klokov@syntacore.com> | 2023-02-27 12:02:28 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-03-14 16:36:30 +1000 |
| commit | 13e269f64aae28b76a9909eed445dfe526086766 (patch) | |
| tree | 38daa5568e40dbff5c97e34998732b5703a4fe0b /disas/riscv.c | |
| parent | 284c52eec2d0a1b9c47f06c3eee46762c5fc0915 (diff) | |
| download | qemu-13e269f64aae28b76a9909eed445dfe526086766.zip qemu-13e269f64aae28b76a9909eed445dfe526086766.tar.gz qemu-13e269f64aae28b76a9909eed445dfe526086766.tar.bz2 | |
disas/riscv: Fix slli_uw decoding
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230227090228.17117-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv.c')
| -rw-r--r-- | disas/riscv.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/disas/riscv.c b/disas/riscv.c index 54455aa..2aca11b 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = { { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, { "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, - { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, + { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 }, { "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, { "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, @@ -2617,10 +2617,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) switch (((inst >> 12) & 0b111)) { case 0: op = rv_op_addiw; break; case 1: - switch (((inst >> 25) & 0b1111111)) { + switch (((inst >> 26) & 0b111111)) { case 0: op = rv_op_slliw; break; - case 4: op = rv_op_slli_uw; break; - case 48: + case 2: op = rv_op_slli_uw; break; + case 24: switch ((inst >> 20) & 0b11111) { case 0b00000: op = rv_op_clzw; break; case 0b00001: op = rv_op_ctzw; break; |