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2024-12-20user: Declare cpu_loop() once in 'user/cpu_loop.h'Philippe Mathieu-Daudé1-1/+1
Declare cpu_loop() once in "user/cpu_loop.h". bsd-user gets the G_NORETURN attribute. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-18-philmd@linaro.org>
2024-10-02bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCVMark Corbin1-0/+54
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn' functions for RISC-V architecture, Both functions ensure that the CPU state and user context are properly managed. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-17-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement 'get_mcontext' for RISC-VMark Corbin1-0/+53
Added the 'get_mcontext' function to extract and populate the RISC-V machine context from the CPU state. This function is used to gather the current state of the general-purpose registers and store it in a 'target_mcontext_' structure. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-16-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V signal trampoline setup functionsMark Corbin1-0/+63
Added functions for setting up the RISC-V signal trampoline and signal frame: 'set_sigtramp_args()': Configures the RISC-V CPU state with arguments for the signal handler. It sets up the registers with the signal number,pointers to the signal info and user context, the signal handler address, and the signal frame pointer. 'setup_sigframe_arch()': Initializes the signal frame with the current machine context.This function copies the context from the CPU state to the signal frame, preparing it for the signal handler. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-15-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V signal handling structures and constantsMark Corbin1-0/+75
Added definitions for RISC-V signal handling, including structures and constants for managing signal frames and context Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-14-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add generic RISC-V64 target definitionsWarner Losh1-0/+20
Added a generic definition for RISC-V64 target-specific details. Implemented the 'regpairs_aligned' function,which returns 'false' to indicate that register pairs are not aligned in the RISC-V64 ABI. Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-13-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V system call structures and constantsMark Corbin1-0/+38
Introduced definitions for the RISC-V system call interface, including the 'target_pt_regs' structure that outlines the register storage layout during a system call. Added constants for hardware machine identifiers. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-12-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V VM parameters and helper functionsMark Corbin1-0/+53
Added definitions for RISC-V VM parameters, including maximum and default sizes for text, data, and stack, as well as address space limits. Implemented helper functions for retrieving and setting specific values in the CPU state, such as stack pointer and return values. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-11-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V thread setup and initialization supportMark Corbin1-0/+47
Implemented functions for setting up and initializing threads in the RISC-V architecture. The 'target_thread_set_upcall' function sets up the stack pointer, program counter, and function argument for new threads. The 'target_thread_init' function initializes thread registers based on the provided image information. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-10-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V sysarch system call emulationMark Corbin1-0/+41
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch' system call for the RISC-V architecture. Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that the operation is not supported. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-9-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V signal trampoline setup functionMark Corbin1-0/+41
Implemented the 'setup_sigtramp' function for setting up the signal trampoline code in the RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-8-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Define RISC-V register structures and register copyingMark Corbin1-0/+88
Added definitions for RISC-V register structures, including general-purpose registers and floating-point registers, in 'target_arch_reg.h'. Implemented the 'target_copy_regs' function to copy register values from the CPU state to the target register structure, ensuring proper endianness handling using 'tswapreg'. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-7-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V ELF definitions and hardware capability detectionMark Corbin1-0/+42
Introduced RISC-V specific ELF definitions and hardware capability detection. Additionally, a function to retrieve hardware capabilities ('get_elf_hwcap') is implemented, which returns the common bits set in each CPU's ISA strings. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-6-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V TLS register setupMark Corbin2-0/+56
Included the prototype for the 'target_cpu_set_tls' function in the 'target_arch.h' header file. This function is responsible for setting the Thread Local Storage (TLS) register for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-5-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V CPU register cloning and reset functionsMark Corbin1-0/+14
Added functions for cloning CPU registers and resetting the CPU state for RISC-V architecture. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Add RISC-V CPU execution loop and syscall handlingMark Corbin1-0/+94
Implemented the RISC-V CPU execution loop, including handling various exceptions and system calls. The loop continuously executes CPU instructions,processes exceptions, and handles system calls by invoking FreeBSD syscall handlers. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Co-authored-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-3-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-02bsd-user: Implement RISC-V CPU initialization and main loopMark Corbin1-0/+40
Added the initial implementation for RISC-V CPU initialization and main loop. This includes setting up the general-purpose registers and program counter based on the provided target architecture definitions. Signed-off-by: Mark Corbin <mark@dibsco.co.uk> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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