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2024-05-30target/arm: Convert SRHADD, URHADD to decodetreeRichard Henderson2-8/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SRHADD, URHADD to gvecRichard Henderson6-98/+158
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SHSUB, UHSUB to decodetreeRichard Henderson2-8/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SHSUB, UHSUB to gvecRichard Henderson6-45/+157
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SHADD, UHADD to decodetreeRichard Henderson2-8/+5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SHADD, UHADD to gvecRichard Henderson6-45/+158
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Use TCG_COND_TSTNE in gen_cmtst_vecRichard Henderson1-3/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64}Richard Henderson1-4/+2
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetreeRichard Henderson2-84/+60
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert ADD, SUB (vector) to decodetreeRichard Henderson2-15/+13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SQRSHL, UQRSHL to decodetreeRichard Henderson2-26/+26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SQRSHL and UQRSHL (register) to gvecRichard Henderson7-72/+71
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SQSHL, UQSHL to decodetreeRichard Henderson2-25/+53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SQSHL and UQSHL (register) to gvecRichard Henderson7-22/+83
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240528203044.612851-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SRSHL, URSHL to decodetreeRichard Henderson2-15/+11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SRSHL and URSHL (register) to gvecRichard Henderson7-23/+84
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240528203044.612851-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SSHL, USHL to decodetreeRichard Henderson2-15/+32
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SUQADD, USQADD to decodetreeRichard Henderson2-58/+14
These are faux 2-operand instructions, reading from rd. Sort them next to the other three-operand same insns for clarity. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetreeRichard Henderson2-43/+64
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUBRichard Henderson5-208/+169
This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Inline scalar SUQADD and USQADDRichard Henderson5-222/+103
This eliminates the last uses of these neon helpers. Incorporate the MO_64 expanders as an option to the vector expander. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Convert SUQADD and USQADD to gvecRichard Henderson5-62/+243
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Assert oprsz in range when using vfp.qcRichard Henderson1-0/+9
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240528203044.612851-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUBRichard Henderson1-16/+16
No need for a full comparison; xor produces non-zero bits for QC just fine. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30arm/sbsa-ref: move to Neoverse-N2 as defaultMarcin Juszkiewicz1-1/+1
Moving to Neoverse-N2 gives us several cpu features to use for expanding our platform: - branch target identification - pointer authentication - RME for confidential computing - RNG for EFI_PROTOCOL_RNG - SVE being enabled by default We do not go for "max" as default to have stable set of features enabled by default. It is still supported and can be selected with "--cpu" argument. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240523165353.6547-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30tests/avocado: update sbsa-ref firmwareMarcin Juszkiewicz1-10/+10
Partial support for NUMA setup: - cpu nodes - memory nodes Used versions: - Trusted Firmware v2.11.0 - Tianocore EDK2 stable202405 - Tianocore EDK2 Platforms code commit 4bbd0ed Firmware is built using Debian 'bookworm' cross toolchain (gcc 12.2.0). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/arm/xilinx_zynq: Support up to two CPU coresSebastian Huber1-21/+33
The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524120837.10057-3-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed unnecessary double-cast] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/arm/xilinx_zynq: Add cache controllerSebastian Huber2-0/+2
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524120837.10057-2-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/intc/arm_gic: Fix writes to GICD_ITARGETSRnSebastian Huber1-0/+7
According to the GICv2 specification section 4.3.12, "Interrupt Processor Targets Registers, GICD_ITARGETSRn": "Any change to a CPU targets field value: [...] * Has an effect on any pending interrupts. This means: - adding a CPU interface to the target list of a pending interrupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524113256.8102-3-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/intc/arm_gic: Fix set pending of PPIsSebastian Huber1-1/+4
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524113256.8102-2-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-29Merge tag 'pull-request-2024-05-29' of https://gitlab.com/thuth/qemu into ↵Richard Henderson16-277/+355
staging * Fix and improve PER emulation on s390x * Fix problems of the build-oss-fuzz CI job * Fix broken update-linux-headers.sh script * Fixes for compiling with -fsanitize=undefined on latest Clang versions # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmZXCNURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU0SxAAnN1i7v/RPfxm1xNQurs+Wl+rS2gJyvGK # IJbEBAYufSQyY4yYrmZrmgNsa3CenPQpV7zWDvUV8BW8R3er8ZGLHmJ3cXQDaN5n # JiLy9rvEBmAVb0LLaQX1GY94jdPRV2mRS9Q7Rxa2XDhn0w+sRy/wNFYEO2nghPjs # zmhbDZrKm8os6imyp0DmDNWi8wLJJzpz8YsKlX60rPEFIynaNdp1ZuB6cXx+9pXH # KXqiY8k/3WCYVs60xB9TfXh2o/Vb29WWaD5IyobZzGEq9pFyQzQf3aqhrv/heRfS # B9537otkU9RIRf09p9f9/78JYHynb3SclM8UXHIGhYQl2S1C9T9gRePO9R+Rigq4 # 51UdsNvZV9WoacVk+L3c2MgIDAXsDOhTSpGKxgWZKgvxhczhr/iOEmWI+oyag7oD # JZfHzwgdwFywumgMrLUrvf6274cyoDNIjpSFnfw0h2Ynp3qkpyigVw5gtP5sfQgD # p/CoVUSRHxsajYQP3UmI70gG1fFbSz2ZWdnG+lC7kkCrD/xD4xLGP9DYK82d1/YS # PmBaVoBttylOtr/S/I8KgJSmaQG0V/Sui7/5iyouZ26VFqakPnNzbxSDlJOEZ7k7 # GigybdjLSy6OWg0IfTOpuxsB3Cw/P2VZrNoO9xUmrjXpdBA/8BCkhmTNYu3QRvS1 # Mwgdyxqdy8I= # =2/Y3 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 29 May 2024 03:52:05 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] * tag 'pull-request-2024-05-29' of https://gitlab.com/thuth/qemu: (22 commits) qapi: Do not cast function pointers lockable: Do not cast function pointers qemu-keymap: Make references to allocations static scripts/update-linux-headers.sh: Fix the path of setup_data.h scripts/update-linux-headers.sh: Remove temporary directory inbetween hw/s390x: Remove unused macro VMSTATE_ADAPTER_ROUTES fuzz: disable leak-detection for oss-fuzz builds fuzz: specify audiodev for usb-audio tests/tcg/s390x: Add per.S target/s390x: Adjust check of noreturn in translate_one target/s390x: Simplify per_ifetch, per_check_exception target/s390x: Fix helper_per_ifetch flags target/s390x: Raise exception from per_store_real target/s390x: Raise exception from helper_per_branch target/s390x: Split per_breaking_event from per_branch_* target/s390x: Simplify help_branch target/s390x: Introduce help_goto_indirect target/s390x: Disable conditional branch-to-next for PER target/s390x: Record separate PER bits in TB flags target/s390x: Update CR9 bits ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-05-29qapi: Do not cast function pointersAkihiko Odaki2-39/+28
Using -fsanitize=undefined with Clang v18 causes an error if function pointers are casted: qapi/qapi-clone-visitor.c:188:5: runtime error: call to function visit_type_SocketAddress through pointer to incorrect function type 'bool (*)(struct Visitor *, const char *, void **, struct Error **)' /tmp/qemu-ubsan/qapi/qapi-visit-sockets.c:487: note: visit_type_SocketAddress defined here #0 0x5642aa2f7f3b in qapi_clone qapi/qapi-clone-visitor.c:188:5 #1 0x5642aa2c8ce5 in qio_channel_socket_listen_async io/channel-socket.c:285:18 #2 0x5642aa2b8903 in test_io_channel_setup_async tests/unit/test-io-channel-socket.c:116:5 #3 0x5642aa2b8204 in test_io_channel tests/unit/test-io-channel-socket.c:179:9 #4 0x5642aa2b8129 in test_io_channel_ipv4 tests/unit/test-io-channel-socket.c:323:5 ... It also prevents enabling the strict mode of CFI which is currently disabled with -fsanitize-cfi-icall-generalize-pointers. The problematic casts are necessary to pass visit_type_T() and visit_type_T_members() as callbacks to qapi_clone() and qapi_clone_members(), respectively. Open-code these two functions to avoid the callbacks, and thus the type casts. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2346 Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-ID: <20240524-xkb-v4-3-2de564e5c859@daynix.com> [thuth: Improve commit message according to Markus' suggestions] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29lockable: Do not cast function pointersAkihiko Odaki1-4/+19
-fsanitize=undefined complains if function pointers are casted. It also prevents enabling the strict mode of CFI which is currently disabled with -fsanitize-cfi-icall-generalize-pointers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2345 Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240524-xkb-v4-2-2de564e5c859@daynix.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29qemu-keymap: Make references to allocations staticAkihiko Odaki1-5/+3
LeakSanitizer complains about allocations whose references are held only by automatic variables. It is possible to free them to suppress the complaints, but it is a chore to make sure they are freed in all exit paths so make them static instead. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240524-xkb-v4-1-2de564e5c859@daynix.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29scripts/update-linux-headers.sh: Fix the path of setup_data.hThomas Huth1-1/+1
When running the update-linx-headers.sh script, it currently fails with: scripts/update-linux-headers.sh: line 73: .../qemu/standard-headers/asm-x86/setup_data.h: No such file or directory The "include" folder is obviously missing here - no clue how this could have worked before? Fixes: 66210a1a30 ("scripts/update-linux-headers: Add setup_data.h to import list") Message-ID: <20240527060126.12578-1-thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29scripts/update-linux-headers.sh: Remove temporary directory inbetweenThomas Huth1-0/+1
We are reusing the same temporary directory for installing the headers of all targets, so there could be stale files here when switching from one target to another. Make sure to delete the folder before installing a new set of target headers into it. Message-ID: <20240527060243.12647-1-thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29hw/s390x: Remove unused macro VMSTATE_ADAPTER_ROUTESThomas Huth1-3/+0
It's not used anywhere, so let's simply remove it. Message-ID: <20240527121351.211266-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29fuzz: disable leak-detection for oss-fuzz buildsAlexander Bulekov1-0/+1
When we are building for OSS-Fuzz, we want to ensure that the fuzzer targets are actually created, regardless of leaks. Leaks will be detected by the subsequent tests of the individual fuzz-targets. Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240527150001.325565-1-alxndr@bu.edu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29fuzz: specify audiodev for usb-audioAlexander Bulekov1-1/+2
Fixes test-failure on Fedora 40 CI. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240527040711.311865-1-alxndr@bu.edu> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29tests/tcg/s390x: Add per.SRichard Henderson2-0/+83
Add a small test to avoid regressions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-15-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Adjust check of noreturn in translate_oneRichard Henderson1-7/+8
If help_op is not set, ret == DISAS_NEXT. Shift the test up from surrounding help_wout, help_cout to skipping to out, as we do elsewhere in the function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-14-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Simplify per_ifetch, per_check_exceptionRichard Henderson3-24/+23
Set per_address and ilen in per_ifetch; this is valid for all PER exceptions and will last until the end of the instruction. Therefore we don't need to give the same data to per_check_exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-13-richard.henderson@linaro.org> [thuth: Silence checkpatch.pl errors] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Fix helper_per_ifetch flagsRichard Henderson1-1/+1
CPU state is read on the exception path. Fixes: 83bb161299c ("target-s390x: PER instruction-fetch nullification event support") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <20240502054417.234340-12-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Raise exception from per_store_realRichard Henderson3-5/+8
At this point the instruction is complete and there's nothing left to do but raise the exception. With this change we need not make two helper calls for this event. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-11-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Raise exception from helper_per_branchRichard Henderson3-38/+27
Drop from argument, since gbea has always been updated with this address. Add ilen argument for setting int_pgm_ilen. Use update_cc_op before calling per_branch. By raising the exception here, we need not call per_check_exception later, which means we can clean up the normal non-exception branch path. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-10-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Split per_breaking_event from per_branch_*Richard Henderson1-3/+3
The breaking-event-address register is updated regardless of PER being enabled. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-9-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Simplify help_branchRichard Henderson1-102/+50
Always use a tcg branch, instead of movcond. The movcond was not a bad idea before PER was added, but since then we have either 2 or 3 actions to perform on each leg of the branch, and multiple movcond is inefficient. Reorder the taken branch to be fallthrough of the tcg branch. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-8-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Introduce help_goto_indirectRichard Henderson1-9/+10
Add a small helper to handle unconditional indirect jumps. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-7-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Disable conditional branch-to-next for PERRichard Henderson1-7/+7
For PER, we require a conditional call to helper_per_branch for the conditional branch. Fold the remaining optimization into a call to helper_goto_direct, which will take care of the remaining gbea adjustment. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240502054417.234340-6-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-29target/s390x: Record separate PER bits in TB flagsRichard Henderson4-35/+62
Record successful-branching, instruction-fetching, and store-using-real-address. The other PER bits are not used during translation. Having checked these at translation time, we can remove runtime tests from the helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240502054417.234340-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2024-08-18 02:42:50 +0000