diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2024-05-28 13:30:34 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-30 15:24:40 +0100 |
| commit | fdaf45d852147f0e565c75b18e1dcedc8af6e767 (patch) | |
| tree | 25487911a121d0b8c90c127f94a3f0289788a137 | |
| parent | 34c0d865a3a29a160f3e572bd49f606cddc56c85 (diff) | |
| download | qemu-fdaf45d852147f0e565c75b18e1dcedc8af6e767.zip qemu-fdaf45d852147f0e565c75b18e1dcedc8af6e767.tar.gz qemu-fdaf45d852147f0e565c75b18e1dcedc8af6e767.tar.bz2 | |
target/arm: Convert SHSUB, UHSUB to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/a64.decode | 2 | ||||
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 11 |
2 files changed, 5 insertions, 8 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index e33d91f..b1bbcb1 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -914,6 +914,8 @@ CMTST_v 0.00 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e CMEQ_v 0.10 1110 ..1 ..... 10001 1 ..... ..... @qrrr_e SHADD_v 0.00 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e UHADD_v 0.10 1110 ..1 ..... 00000 1 ..... ..... @qrrr_e +SHSUB_v 0.00 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e +UHSUB_v 0.10 1110 ..1 ..... 00100 1 ..... ..... @qrrr_e ### Advanced SIMD scalar x indexed element diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 63f7a59..6571b99 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -5456,6 +5456,8 @@ TRANS(ADD_v, do_gvec_fn3, a, tcg_gen_gvec_add) TRANS(SUB_v, do_gvec_fn3, a, tcg_gen_gvec_sub) TRANS(SHADD_v, do_gvec_fn3_no64, a, gen_gvec_shadd) TRANS(UHADD_v, do_gvec_fn3_no64, a, gen_gvec_uhadd) +TRANS(SHSUB_v, do_gvec_fn3_no64, a, gen_gvec_shsub) +TRANS(UHSUB_v, do_gvec_fn3_no64, a, gen_gvec_uhsub) static bool do_cmop_v(DisasContext *s, arg_qrrr_e *a, TCGCond cond) { @@ -10923,7 +10925,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } /* fall through */ case 0x2: /* SRHADD, URHADD */ - case 0x4: /* SHSUB, UHSUB */ case 0xc: /* SMAX, UMAX */ case 0xd: /* SMIN, UMIN */ case 0xe: /* SABD, UABD */ @@ -10949,6 +10950,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) case 0x0: /* SHADD, UHADD */ case 0x01: /* SQADD, UQADD */ + case 0x04: /* SHSUB, UHSUB */ case 0x05: /* SQSUB, UQSUB */ case 0x06: /* CMGT, CMHI */ case 0x07: /* CMGE, CMHS */ @@ -10967,13 +10969,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { - case 0x04: /* SHSUB, UHSUB */ - if (u) { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_uhsub, size); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_shsub, size); - } - return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); |