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2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé6-76/+76
The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1Philippe Mathieu-Daudé3-30/+30
The MIPS ISA release '1' is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-12-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé5-9/+7
Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5Philippe Mathieu-Daudé1-2/+1
Use the single ISA_MIPS32R5 definition to check if the Release 5 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R5 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-10-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3Philippe Mathieu-Daudé1-2/+1
Use the single ISA_MIPS32R3 definition to check if the Release 3 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R3 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-9-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé3-5/+3
Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1Philippe Mathieu-Daudé2-7/+6
Use the single ISA_MIPS32 definition to check if the Release 1 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R1 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-7-f4bug@amsat.org>
2021-01-14hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()Philippe Mathieu-Daudé1-4/+2
Directly check if the CPU supports 64-bit with the recently added cpu_type_is_64bit() helper (inlined). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-6-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()Philippe Mathieu-Daudé2-1/+8
MIPS 64-bit ISA is introduced with MIPS3. Introduce the CPU_MIPS64 definition aliased to the MIPS3 ISA, and the cpu_type_is_64bit() method to check if a CPU supports this ISA (thus is 64-bit). Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-5-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1Philippe Mathieu-Daudé2-11/+11
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing the "Release 1" ISA. Rename it with the 'R1' suffix, as the other CPU definitions do. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Reorder CPU_MIPS5 definitionPhilippe Mathieu-Daudé1-2/+1
Move CPU_MIPS5 after CPU_MIPS4 :) Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-3-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS commentPhilippe Mathieu-Daudé1-6/+0
Remove a comment added 12 years ago but never used (commit b6d96beda3a: "Use temporary registers for the MIPS FPU emulation"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210104221154.3127610-2-f4bug@amsat.org>
2021-01-14target/mips/addr: Add translation helpers for KSEG1Jiaxun Yang2-0/+12
It's useful for bootloader to do I/O operations. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@kernel.org> Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-01-14target/mips: Replace CP0_Config0 magic values by proper definitionsPhilippe Mathieu-Daudé1-6/+8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
2021-01-14target/mips: Add CP0 Config0 register definitions for MIPS3 ISAPhilippe Mathieu-Daudé1-1/+9
The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
2021-01-14Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' ↵Peter Maydell21-668/+889
into staging Improvements to tcg constant handling. Force utf8 for decodetree. # gpg: Signature made Thu 14 Jan 2021 02:15:42 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210113: (24 commits) decodetree: Open files with encoding='utf-8' tcg/aarch64: Use tcg_constant_vec with tcg vec expanders tcg/ppc: Use tcg_constant_vec with tcg vec expanders tcg: Remove tcg_gen_dup{8,16,32,64}i_vec tcg/i386: Use tcg_constant_vec with tcg vec expanders tcg: Add tcg_reg_alloc_dup2 tcg: Remove movi and dupi opcodes tcg/tci: Add special tci_movi_{i32,i64} opcodes tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders tcg: Use tcg_constant_{i32,i64} with tcg plugins tcg: Use tcg_constant_{i32,i64} with tcg int expanders tcg: Use tcg_constant_i32 with icount expander tcg: Convert tcg_gen_dupi_vec to TCG_CONST tcg/optimize: Use tcg_constant_internal with constant folding tcg/optimize: Adjust TempOptInfo allocation tcg/optimize: Improve find_better_copy tcg: Introduce TYPE_CONST temporaries tcg: Expand TempOptInfo to 64-bits tcg: Rename struct tcg_temp_info to TempOptInfo tcg: Expand TCGTemp.val to 64-bits ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-13Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20210113' ↵Peter Maydell6-126/+104
into staging qemu-macppc updates # gpg: Signature made Wed 13 Jan 2021 13:02:20 GMT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-macppc-20210113: macio: don't set user_creatable to false macio: wire macio GPIOs to OpenPIC using sysbus IRQs macio: move OpenPIC inside macio-newworld device mac_newworld: delay wiring of PCI IRQs in New World machine macio: move heathrow PIC inside macio-oldworld device mac_oldworld: move initialisation of grackle before heathrow mac_oldworld: remove duplicate bus check for PPC_INPUT(env) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-13decodetree: Open files with encoding='utf-8'Philippe Mathieu-Daudé1-3/+6
When decodetree.py was added in commit 568ae7efae7, QEMU was using Python 2 which happily reads UTF-8 files in text mode. Python 3 requires either UTF-8 locale or an explicit encoding passed to open(). Now that Python 3 is required, explicit UTF-8 encoding for decodetree source files. To avoid further problems with the user locale, also explicit UTF-8 encoding for the generated C files. Explicit both input/output are plain text by using the 't' mode. This fixes: $ /usr/bin/python3 scripts/decodetree.py test.decode Traceback (most recent call last): File "scripts/decodetree.py", line 1397, in <module> main() File "scripts/decodetree.py", line 1308, in main parse_file(f, toppat) File "scripts/decodetree.py", line 994, in parse_file for line in f: File "/usr/lib/python3.6/encodings/ascii.py", line 26, in decode return codecs.ascii_decode(input, self.errors)[0] UnicodeDecodeError: 'ascii' codec can't decode byte 0xc3 in position 80: ordinal not in range(128) Reported-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Yonggang Luo <luoyonggang@gmail.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210110000240.761122-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/aarch64: Use tcg_constant_vec with tcg vec expandersRichard Henderson1-5/+5
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to "t1 = -v2, t2 = c - v2". This avoids a serial dependency between t1 and t2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/ppc: Use tcg_constant_vec with tcg vec expandersRichard Henderson1-17/+27
Improve expand_vec_shi to use sign-extraction for MO_32. This allows a single VSPLTISB instruction to load all of the valid shift constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Remove tcg_gen_dup{8,16,32,64}i_vecRichard Henderson2-24/+0
These interfaces have been replaced by tcg_gen_dupi_vec and tcg_constant_vec. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/i386: Use tcg_constant_vec with tcg vec expandersRichard Henderson1-13/+13
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Add tcg_reg_alloc_dup2Richard Henderson1-0/+97
There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Remove movi and dupi opcodesRichard Henderson13-45/+1
These are now completely covered by mov from a TYPE_CONST temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/tci: Add special tci_movi_{i32,i64} opcodesRichard Henderson3-4/+12
The normal movi opcodes are going away. We need something for TCI to use internally. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Use tcg_constant_{i32,i64,vec} with gvec expandersRichard Henderson3-77/+59
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Use tcg_constant_{i32,i64} with tcg pluginsRichard Henderson1-27/+22
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Use tcg_constant_{i32,i64} with tcg int expandersRichard Henderson2-131/+109
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Use tcg_constant_i32 with icount expanderRichard Henderson1-12/+13
We must do this before we adjust tcg_out_movi_i32, lest the under-the-hood poking that we do for icount be broken. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Convert tcg_gen_dupi_vec to TCG_CONSTRichard Henderson3-40/+15
Because we now store uint64_t in TCGTemp, we can now always store the full 64-bit duplicate immediate. So remove the difference between 32- and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/optimize: Use tcg_constant_internal with constant foldingRichard Henderson1-59/+49
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/optimize: Adjust TempOptInfo allocationRichard Henderson1-26/+34
Do not allocate a large block for indexing. Instead, allocate for each temporary as they are seen. In general, this will use less memory, if we consider that most TBs do not touch every target register. This also allows us to allocate TempOptInfo for new temps created during optimization. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg/optimize: Improve find_better_copyRichard Henderson1-15/+12
Prefer TEMP_CONST over anything else. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Introduce TYPE_CONST temporariesRichard Henderson3-50/+211
These will hold a single constant for the duration of the TB. They are hashed, so that each value has one temp across the TB. Not used yet, this is all infrastructure. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Expand TempOptInfo to 64-bitsRichard Henderson1-19/+21
This propagates the extended value of TCGTemp.val that we did before. In addition, it will be required for vector constants. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Rename struct tcg_temp_info to TempOptInfoRichard Henderson1-16/+16
Fix this name vs our coding style. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Expand TCGTemp.val to 64-bitsRichard Henderson2-2/+2
This will reduce the differences between 32-bit and 64-bit hosts, allowing full 64-bit constants to be created with the same interface. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Add temp_readonlyRichard Henderson2-11/+15
In most, but not all, places that we check for TEMP_FIXED, we are really testing that we do not modify the temporary. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Consolidate 3 bits into enum TCGTempKindRichard Henderson3-62/+92
The temp_fixed, temp_global, temp_local bits are all related. Combine them into a single enumeration. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Increase tcg_out_dupi_vec immediate to int64_tRichard Henderson4-33/+69
While we don't store more than tcg_target_long in TCGTemp, we shouldn't be limited to that for code generation. We will be able to use this for INDEX_op_dup2_vec with 2 constants. Also pass along the minimal vece that may be said to apply to the constant. This allows some simplification in the various backends. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13tcg: Use tcg_out_dupi_vec from temp_loadRichard Henderson4-34/+46
Having dupi pass though movi is confusing and arguably wrong. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-13Merge remote-tracking branch 'remotes/armbru/tags/pull-yank-2021-01-13' into ↵Peter Maydell17-64/+625
staging Yank patches patches for 2021-01-13 # gpg: Signature made Wed 13 Jan 2021 09:25:46 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-yank-2021-01-13: tests/test-char.c: Wait for the chardev to connect in char_socket_client_dupid_test io: Document qmp oob suitability of qio_channel_shutdown and io_shutdown io/channel-tls.c: make qio_channel_tls_shutdown thread-safe migration: Add yank feature chardev/char-socket.c: Add yank feature block/nbd.c: Add yank feature Introduce yank feature Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-13macio: don't set user_creatable to falseMark Cave-Ayland1-2/+0
Now that all of the object property links to the heathrow PIC and OpenPIC have been removed from the macio devices, it is safe to allow the macio-oldworld and macio-neworld devices to be marked as user_creatable. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20201229175619.6051-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13macio: wire macio GPIOs to OpenPIC using sysbus IRQsMark Cave-Ayland3-26/+12
This both allows the wiring to be done as Ben suggested in his original comment in gpio.c and also enables the OpenPIC object property link to be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20201229175619.6051-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13macio: move OpenPIC inside macio-newworld deviceMark Cave-Ayland3-25/+21
The OpenPIC device is located within the macio device on real hardware so make it a child of the macio-newworld device. This also removes the need for setting and checking a separate PIC object property link on the macio-newworld device which currently causes the automated QOM introspection tests to fail. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13mac_newworld: delay wiring of PCI IRQs in New World machineMark Cave-Ayland1-20/+26
In order to move the OpenPIC device to the macio device, the PCI bus needs to be initialised before the macio device and also before wiring the OpenPIC IRQs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13macio: move heathrow PIC inside macio-oldworld deviceMark Cave-Ayland3-45/+43
The heathrow PIC is located within the macio device on real hardware so make it a child of the macio-oldworld device. This also removes the need for setting and checking a separate PIC object property link on the macio-oldworld device which currently causes the automated QOM introspection tests to fail. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13mac_oldworld: move initialisation of grackle before heathrowMark Cave-Ayland1-15/+15
In order to move the heathrow PIC to the macio device, the PCI bus needs to be initialised before the macio device and also before wiring the PIC IRQs. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13mac_oldworld: remove duplicate bus check for PPC_INPUT(env)Mark Cave-Ayland1-6/+0
This condition will have already been caught when wiring the heathrow PIC IRQs to the CPU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20201229175619.6051-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2021-01-13tests/test-char.c: Wait for the chardev to connect in ↵Lukas Straub1-0/+1
char_socket_client_dupid_test A connecting chardev object has an additional reference by the connecting thread, so if the chardev is still connecting by the end of the test, then the chardev object won't be freed. This in turn means that the yank instance won't be unregistered and when running the next test-case yank_register_instance will abort, because the yank instance is already/still registered. Signed-off-by: Lukas Straub <lukasstraub2@web.de> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <1445e97a5800e3f2ba024ad52b500a0315701632.1609167865.git.lukasstraub2@web.de> Signed-off-by: Markus Armbruster <armbru@redhat.com>
generated by cgit v1.1 at 2024-08-18 08:19:24 +0000