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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-01 12:29:22 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | 8cd0b410a24159891809ba5f41fa55abb5adf196 (patch) | |
| tree | eebb4695edc7ab0d6edc156e017b13d75228b09a | |
| parent | 7c79721606be11b5bc556449e5bcbc331ef6867d (diff) | |
| download | qemu-8cd0b410a24159891809ba5f41fa55abb5adf196.zip qemu-8cd0b410a24159891809ba5f41fa55abb5adf196.tar.gz qemu-8cd0b410a24159891809ba5f41fa55abb5adf196.tar.bz2 | |
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
| -rw-r--r-- | target/mips/cpu.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4cbc31c..0086f95 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -828,7 +828,7 @@ struct CPUMIPSState { #define CP0EBase_WG 11 target_ulong CP0_CMGCRBase; /* - * CP0 Register 16 + * CP0 Register 16 (after Release 1) */ int32_t CP0_Config0; #define CP0C0_M 31 @@ -845,6 +845,14 @@ struct CPUMIPSState { #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ #define CP0C0_AR_LENGTH 3 +/* + * CP0 Register 16 (before Release 1) + */ +#define CP0C0_Impl 16 /* 24..16 */ +#define CP0C0_IC 9 /* 11..9 */ +#define CP0C0_DC 6 /* 8..6 */ +#define CP0C0_IB 5 +#define CP0C0_DB 4 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ |