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2020-09-01target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisonsPeter Maydell3-3/+56
Convert the Neon floating-point vector comparison ops VCEQ, VCGE and VCGT over to using a gvec helper and use this to implement the fp16 case. (We put the float16_ceq() etc functions above the DO_2OP() macro definition because later when we convert the compare-against-zero instructions we'll want their definitions to be visible at that point in the source file.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-27-peter.maydell@linaro.org
2020-09-01target/arm: Implement fp16 for Neon VABS, VNEG of floatsPeter Maydell1-6/+28
Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so that we can implement the fp16 version of the insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-26-peter.maydell@linaro.org
2020-09-01target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvecPeter Maydell1-2/+29
We already have gvec helpers for floating point VRECPE and VRQSRTE, so convert the Neon decoder to use them and add the fp16 support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-25-peter.maydell@linaro.org
2020-09-01target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMULPeter Maydell3-17/+26
Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC macro: VADD, VSUB, VABD, VMUL. For VABD this requires us to implement a new gvec_fabd_h helper using the machinery we have already for the other helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-24-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VMOV between gp and halfprec registersPeter Maydell2-0/+35
Implement the VFP fp16 variant of VMOV that transfers a 16-bit value between a general purpose register and a VFP register. Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later only we have no need to replicate the old "updates CPSR.NZCV" behaviour that the singleprec version of this insn does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-22-peter.maydell@linaro.org
2020-09-01target/arm: Implement new VFP fp16 insn VMOVXPeter Maydell2-0/+28
The fp16 extension includes a new instruction VMOVX, which copies the upper 16 bits of a 32-bit source VFP register into the lower 16 bits of the destination and zeroes the high half of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
2020-09-01target/arm: Implement new VFP fp16 insn VINSPeter Maydell2-0/+31
The fp16 extension includes a new instruction VINS, which copies the lower 16 bits of a 32-bit source VFP register into the upper 16 bits of the destination. Implement it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-20-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VRINT*Peter Maydell5-8/+122
Implement the fp16 version of the VFP VRINT* insns. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-19-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VSELPeter Maydell2-6/+16
Implement the fp16 versions of the VFP VSEL instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-18-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP vp16 VCVT-with-specified-rounding-modePeter Maydell2-10/+28
Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer with a specified rounding mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-17-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VCVT between float and fixed-pointPeter Maydell2-0/+61
Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-16-peter.maydell@linaro.org
2020-09-01target/arm: Use macros instead of open-coding fp16 conversion helpersPeter Maydell2-80/+12
Now the VFP_CONV_FIX macros can handle fp16's distinction between the width of the operation and the width of the type used to pass operands, use the macros rather than the open-coded functions. This creates an extra six helper functions, all of which we are going to need for the AArch32 VFP fp16 instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-15-peter.maydell@linaro.org
2020-09-01target/arm: Make VFP_CONV_FIX macros take separate float type and float sizePeter Maydell1-23/+23
Currently the VFP_CONV_FIX macros take a single fsz argument for the size of the float type, which is used both to select the name of the functions to call (eg float32_is_any_nan()) and also for the type to use for the float inputs and outputs (eg float32). Separate these into fsz and ftype arguments, so that we can use them for fp16, which uses 'float16' in the function names but is still passing inputs and outputs in a 32-bit sized type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-14-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VCVT between float and integerPeter Maydell2-0/+69
Implement the fp16 versions of the VFP VCVT instruction forms which convert between floating point and integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-13-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VLDR and VSTRPeter Maydell2-2/+36
Implement the fp16 versions of the VFP VLDR/VSTR (immediate). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-12-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VCMPPeter Maydell4-7/+51
Implement fp16 version of VCMP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-11-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 for VMOV immediatePeter Maydell2-0/+24
Implement VFP fp16 support for the VMOV immediate insn. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-10-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 for VABS, VNEG, VSQRTPeter Maydell4-0/+55
Implement VFP fp16 for VABS, VNEG and VSQRT. This is all the fp16 insns that use the DO_VFP_2OP macro, because there is no fp16 version of VMOV_reg. Notes: * the gen_helper_vfp_negh already exists as we needed to create it for the fp16 multiply-add insns * as usual we need to use the f16 version of the fp_status; this is only relevant for VSQRT Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-9-peter.maydell@linaro.org
2020-09-01target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()Peter Maydell1-35/+14
Macroify the uses of do_vfp_2op_sp() and do_vfp_2op_dp(); this will make it easier to add the halfprec support. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-8-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 for fused-multiply-addPeter Maydell4-0/+77
Implement VFP fp16 support for fused multiply-add insns VFNMA, VFNMS, VFMA, VFMS. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-7-peter.maydell@linaro.org
2020-09-01target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMSPeter Maydell1-37/+13
Macroify creation of the trans functions for single and double precision VFMA, VFMS, VFNMA, VFNMS. The repetition was OK for two sizes, but we're about to add halfprec and it will get a bit more than seems reasonable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-6-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMULPeter Maydell4-0/+95
Implement fp16 versions of the VFP VMLA, VMLS, VNMLS, VNMLA, VNMUL instructions. (These are all the remaining ones which we implement via do_vfp_3op_[hsd]p().) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-5-peter.maydell@linaro.org
2020-09-01target/arm: Implement VFP fp16 for VFP_BINOP operationsPeter Maydell5-0/+106
Implmeent VFP fp16 support for simple binary-operator VFP insns VADD, VSUB, VMUL, VDIV, VMINNM and VMAXNM: * make the VFP_BINOP() macro generate float16 helpers as well as float32 and float64 * implement a do_vfp_3op_hp() function similar to the existing do_vfp_3op_sp() * add decode for the half-precision insn patterns Note that the VFP_BINOP macro use creates a couple of unused helper functions vfp_maxh and vfp_minh, but they're small so it's not worth splitting the BINOP operations into "needs halfprec" and "no halfprec" groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-4-peter.maydell@linaro.org
2020-09-01target/arm: Use correct ID register check for aa32_fp16_arithPeter Maydell1-6/+1
The aa32_fp16_arith feature check function currently looks at the AArch64 ID_AA64PFR0 register. This is (as the comment notes) not correct. The bogus check was put in mostly to allow testing of the fp16 variants of the VCMLA instructions and it was something of a mistake that we allowed them to exist in master. Switch the feature check function to testing VMFR1.FPHP, which is what it ought to be. This will remove emulation of the VCMLA and VCADD insns from AArch32 code running on an AArch64 '-cpu max' using system emulation. (They were never enabled for aarch32 linux-user and system-emulation.) Since we weren't advertising their existence via the AArch32 ID register, well-behaved guests wouldn't have been using them anyway. Once we have implemented all the AArch32 support for the FP16 extension we will advertise it in the MVFR1 ID register field, which will reenable these insns along with all the others. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-3-peter.maydell@linaro.org
2020-09-01target/arm: Remove local definitions of float constantsPeter Maydell3-19/+0
In several places the target/arm code defines local float constants for 2, 3 and 1.5, which are also provided by include/fpu/softfloat.h. Remove the unnecessary local duplicate versions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200828183354.27913-2-peter.maydell@linaro.org
2020-09-01docs/system: Fix grammar in documentationStefan Weil1-3/+3
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200827173051.31050-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01main-loop: Fix commentStefan Weil1-1/+1
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200827175520.32355-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/display/vga:Remove redundant statement in vga_draw_graphic()Chen Qun1-1/+0
Clang static code analyzer show warning: hw/display/vga.c:1677:9: warning: Value stored to 'update' is never read update = full_update; ^ ~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200827110311.164316-11-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/intc: fix default registers value in exynos4210_combiner_read()Chen Qun1-1/+0
Clang static code analyzer show warning: hw/intc/exynos4210_combiner.c:231:9: warning: Value stored to 'val' is never read val = s->reg_set[offset >> 2]; The default register return value should be return 'val'. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200827110311.164316-10-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01usb/bus: Remove dead assignment in usb_get_fw_dev_path()Chen Qun1-2/+2
Clang static code analyzer show warning: qemu/hw/usb/bus.c:615:13: warning: Value stored to 'pos' is never read pos += snprintf(fw_path + pos, fw_len - pos, "%s@%lx", Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20200827110311.164316-9-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01vfio/platform: Remove dead assignment in vfio_intp_interrupt()Chen Qun1-1/+1
Clang static code analyzer show warning: hw/vfio/platform.c:239:9: warning: Value stored to 'ret' is never read ret = event_notifier_test_and_clear(intp->interrupt); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200827110311.164316-8-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/net/virtio-net:Remove redundant statement in virtio_net_rsc_tcp_ctrl_check()Chen Qun1-1/+0
Clang static code analyzer show warning: hw/net/virtio-net.c:2077:5: warning: Value stored to 'tcp_flag' is never read tcp_flag &= VIRTIO_NET_TCP_FLAG; ^ ~~~~~~~~~~~~~~~~~~~ The 'VIRTIO_NET_TCP_FLAG' is '0x3F'. The last ‘tcp_flag’ assignment statement is the same as that of the first two statements. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20200827110311.164316-7-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/virtio/vhost-user:Remove dead assignment in scrub_shadow_regions()Chen Qun1-1/+1
Clang static code analyzer show warning: hw/virtio/vhost-user.c:606:9: warning: Value stored to 'mr' is never read mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20200827110311.164316-6-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01target/arm/translate-a64:Remove redundant statement in ↵Chen Qun1-3/+0
disas_simd_two_reg_misc_fp16() Clang static code analyzer show warning: target/arm/translate-a64.c:13007:5: warning: Value stored to 'rd' is never read rd = extract32(insn, 0, 5); ^ ~~~~~~~~~~~~~~~~~~~~~ target/arm/translate-a64.c:13008:5: warning: Value stored to 'rn' is never read rn = extract32(insn, 5, 5); ^ ~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200827110311.164316-5-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01target/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli()Chen Qun1-2/+2
Clang static code analyzer show warning: target/arm/translate-a64.c:8635:14: warning: Value stored to 'tcg_rn' during its initialization is never read TCGv_i64 tcg_rn = new_tmp_a64(s); ^~~~~~ ~~~~~~~~~~~~~~ target/arm/translate-a64.c:8636:14: warning: Value stored to 'tcg_rd' during its initialization is never read TCGv_i64 tcg_rd = new_tmp_a64(s); ^~~~~~ ~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200827110311.164316-4-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/arm/omap1:Remove redundant statement in omap_clkdsp_read()Chen Qun1-1/+0
Clang static code analyzer show warning: hw/arm/omap1.c:1760:15: warning: Value stored to 'cpu' during its initialization is never read CPUState *cpu = CPU(s->cpu); ^~~ ~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200827110311.164316-3-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/arm/virt-acpi-build:Remove dead assignment in build_madt()Chen Qun1-2/+1
Clang static code analyzer show warning: hw/arm/virt-acpi-build.c:641:5: warning: Value stored to 'madt' is never read madt = acpi_data_push(table_data, sizeof *madt); ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20200827110311.164316-2-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01linux-user: Add strace support for printing OFD fcntl operationsMike Gelfand1-0/+12
Signed-off-by: Mike Gelfand <mikedld@mikedld.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200830092242.31506-1-mikedld@mikedld.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01util/vfio-helpers: Unify trace-events size formatPhilippe Mathieu-Daudé1-3/+3
Some 'qemu_vfio_*' trace events sizes are displayed using decimal notation, other using hexadecimal notation: qemu_vfio_ram_block_added s 0xaaaaf2448d90 host 0xffff5bc00000 size 0x4000000 qemu_vfio_dma_map s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 temporary 0 iova (nil) qemu_vfio_find_mapping s 0xaaaaf2448d90 host 0xffff5bc00000 qemu_vfio_new_mapping s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 index 4 iova 0x114000 qemu_vfio_do_mapping s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 iova 0x114000 As it is hard to follow, unify using hexadecimal for all sizes: qemu_vfio_ram_block_added s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 qemu_vfio_dma_map s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 temporary 0 iova (nil) qemu_vfio_find_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000 qemu_vfio_new_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 index 4 iova 0x114000 qemu_vfio_do_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 iova 0x114000 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Message-Id: <20200820171006.1140228-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/net/xilinx_axienet: Remove unused codePhilippe Mathieu-Daudé1-23/+0
Most of the MDIOBus fields are unused. The ADVERTISE_10HALF definition is unused. Remove unused code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-Id: <20200814133007.16850-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/scsi/scsi-disk: Replace magic '512' value by BDRV_SECTOR_SIZEPhilippe Mathieu-Daudé1-21/+23
Use self-explicit definitions instead of magic '512' value. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200814082841.27000-8-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZEPhilippe Mathieu-Daudé1-1/+1
Use self-explicit definitions instead of magic '512' value. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200814082841.27000-7-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZEPhilippe Mathieu-Daudé1-4/+4
Use self-explicit definitions instead of magic '512' value. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200814082841.27000-6-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZEPhilippe Mathieu-Daudé1-2/+3
Use self-explicit definitions instead of magic '512' value. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200814082841.27000-5-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/ide/core: Trivial typo fixPhilippe Mathieu-Daudé1-1/+1
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20200814082841.27000-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01docs/system/target-avr: Improve the AVR docs and add to MAINTAINERSThomas Huth2-18/+30
The examples look nicer when using "::" code blocks. Also mention that "-d in_asm" only outputs instructions that have not been translated by the JIT layer yet. And while we're at it, also add the AVR doc file to the MAINTAINERS file. Signed-off-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael Rolnik <mrolnik@gmail.com> Message-Id: <20200812155304.18016-1-huth@tuxfamily.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01mailmap: Add entry for Greg KurzGreg Kurz1-0/+1
I had stopped using gkurz@linux.vnet.ibm.com a while back already but this email address was shutdown last June when I quit IBM. It's about time to map it to groug@kaod.org. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <159724665142.75339.817685642171828648.stgit@bahia.lan> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01util/vfio-helpers: Fix typo in descriptionPhilippe Mathieu-Daudé1-2/+2
Remove the second 'and' introduced in commit 418026ca43 ("util: Introduce vfio helpers"). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200811151643.21293-4-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01util/qemu-timer: Fix typo in descriptionPhilippe Mathieu-Daudé1-1/+1
Remove the second 'and' introduced in commit e81f86790f ("qemu-timer: avoid checkpoints for virtual clock timers in external subsystems"). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200811151643.21293-3-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-01hw/i2c: Fix typo in descriptionPhilippe Mathieu-Daudé1-1/+1
Remove the second 'and' introduced in commit 73d5f22ecb ("hw/i2c: Document the I2C qdev helpers"). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Li Qiang <liq3ea@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200811151643.21293-2-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.1 at 2025-01-27 11:08:21 +0000