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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 19:33:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-09-01 11:19:32 +0100 |
| commit | e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e (patch) | |
| tree | 9004894b12b67e2e67f34d52dbc645a128f6afb4 | |
| parent | 0a6f4b4cb338665b81ad824d9a6868932461b7f7 (diff) | |
| download | qemu-e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e.zip qemu-e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e.tar.gz qemu-e4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e.tar.bz2 | |
target/arm: Implement new VFP fp16 insn VINS
The fp16 extension includes a new instruction VINS, which copies the
lower 16 bits of a 32-bit source VFP register into the upper 16 bits
of the destination. Implement it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-20-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/translate-vfp.c.inc | 28 | ||||
| -rw-r--r-- | target/arm/vfp-uncond.decode | 3 |
2 files changed, 31 insertions, 0 deletions
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 7ce044f..bda3dd2 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3454,3 +3454,31 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a) return false; } + +static bool trans_VINS(DisasContext *s, arg_VINS *a) +{ + TCGv_i32 rd, rm; + + if (!dc_isar_feature(aa32_fp16_arith, s)) { + return false; + } + + if (s->vec_len != 0 || s->vec_stride != 0) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Insert low half of Vm into high half of Vd */ + rm = tcg_temp_new_i32(); + rd = tcg_temp_new_i32(); + neon_load_reg32(rm, a->vm); + neon_load_reg32(rd, a->vd); + tcg_gen_deposit_i32(rd, rd, rm, 16, 16); + neon_store_reg32(rd, a->vd); + tcg_temp_free_i32(rm); + tcg_temp_free_i32(rd); + return true; +} diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 9615544..39dc8f6 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -74,3 +74,6 @@ VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ vm=%vm_sp vd=%vd_sp sz=2 VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ vm=%vm_dp vd=%vd_sp sz=3 + +VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \ + vd=%vd_sp vm=%vm_sp |