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2019-06-07s390x/tcg: Implement VECTOR FP SQUARE ROOTDavid Hildenbrand4-0/+40
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATIONDavid Hildenbrand2-0/+54
The only FP instruction we can implement without an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT)David Hildenbrand4-0/+79
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP MULTIPLYDavid Hildenbrand4-0/+24
Very similar to VECTOR FP DIVIDE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD ROUNDEDDavid Hildenbrand4-0/+50
We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD LENGTHENEDDavid Hildenbrand4-0/+58
Take care of reading/indicating the 32-bit elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR LOAD FP INTEGERDavid Hildenbrand4-0/+30
We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP DIVIDEDavid Hildenbrand4-0/+24
We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BITDavid Hildenbrand4-0/+30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BITDavid Hildenbrand4-0/+30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BITDavid Hildenbrand4-0/+30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BITDavid Hildenbrand4-0/+76
1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL)David Hildenbrand4-0/+173
Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALARDavid Hildenbrand4-0/+59
As far as I can see, there is only a tiny difference. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FP ADDDavid Hildenbrand5-0/+158
1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask()David Hildenbrand2-2/+6
Vector floating-point instructions will require these functions, so allow to use them from other files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Introduce tcg_s390_vector_exception()David Hildenbrand3-0/+18
Handling is similar to data exceptions, however we can always store the VXC into the lowore and the FPC: z14 PoP, 6-20, "Vector-Exception Code" When a vector-processing exception causes a pro- gram interruption, a vector-exception code (VXC) is stored at location 147, and zeros are stored at loca- tions 144-146. The VXC is also placed in the DXC field of the floating-point-control (FPC) register if bit 45 of control register 0 is one. When bit 45 of control register 0 is zero and bit 46 of control register 0 is one, the DXC field of the FPC register and the con- tents of storage at location 147 are unpredictable. Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Store only the necessary amount of doublewords for STFLEDavid Hildenbrand1-1/+7
The PoP (z14, 7-382) says: Doublewords to the right of the doubleword in which the highest-numbered facility bit is assigned for a model may or may not be stored. However, stack protection in certain binaries can't deal with that. "gzip" example code: f1b4: a7 08 00 03 lhi %r0,3 f1b8: b2 b0 f0 a0 stfle 160(%r15) f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15) f1c2: c0 2b 00 00 00 01 nilf %r2,1 f1c8: b2 4f 00 10 ear %r1,%a0 f1cc: b9 14 00 22 lgfr %r2,%r2 f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32 f1d6: b2 4f 00 11 ear %r1,%a1 f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1) f1e0: a7 74 00 06 jne f1ec <file_read@@Base+0x1bc> f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15) f1ea: 07 fe br %r14 f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt> In QEMU, we currently have: max_bytes = 24 the code asks for (3 + 1) doublewords == 32 bytes. If we write 32 bytes instead of only 24, and return "2 + 1" doublewords ("one less than the number of doulewords needed to contain all of the facility bits"), the example code detects a stack corruption. In my opinion, the code is wrong. However, it seems to work fine on real machines. So let's limit storing to the minimum of the requested and the maximum doublewords. Cc: Stefan Liebler <stli@linux.ibm.com> Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Fix max_byte detection for stfleDavid Hildenbrand1-1/+2
used_stfl_bytes is 0, before initialized via prepare_stfl() on the first invocation. We have to move the calculation of max_bytes after prepare_stfl(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Use uint64_t for vector registersDavid Hildenbrand9-97/+97
CPU_DoubleU is primarily used to reinterpret between integer and floats. We don't really need this functionality. So let's just keep it simple and use an uint64_t. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x: Align vector registers to 16 bytesDavid Hildenbrand1-1/+1
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store") revealed that the vregs are not aligned to 16 bytes. Align them to 16 bytes, to avoid segfault'ing on x86. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR STRING RANGE COMPAREDavid Hildenbrand5-0/+237
Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR ISOLATE STRINGDavid Hildenbrand4-0/+87
Logic mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT NOT EQUALDavid Hildenbrand5-0/+132
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ELEMENT EQUALDavid Hildenbrand4-0/+96
Core logic courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07s390x/tcg: Implement VECTOR FIND ANY ELEMENT EQUALDavid Hildenbrand5-1/+198
Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07MAINTAINERS: cover tests/migration/s390x/Cornelia Huck1-0/+1
The generic s390 section looks like the best resting place. Message-Id: <20190529091243.25562-1-cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-07Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-7-2019' ↵Peter Maydell239-197/+6550
into staging MIPS Queue for June 7th, 2019 # gpg: Signature made Fri 07 Jun 2019 10:59:15 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-7-2019: tests/tcg: target/mips: Add README for MSA tests tests/tcg: target/mips: Add tests for MSA FP max/min instructions tests/tcg: target/mips: Add utility function reset_msa_registers() tests/tcg: target/mips: Move four tests to a better location tests/tcg: target/mips: Add tests for MSA shift instructions tests/tcg: target/mips: Amend and rearrange MSA wrappers target/mips: Unroll loops in helpers for MSA logic instructions target/mips: Outline places for future MSA helpers target/mips: Fix block-comment-related issues in msa_helper.c target/mips: Fix space-related format issues in msa_helper.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-07tests/tcg: target/mips: Add README for MSA testsAleksandar Markovic3-0/+904
Add README for MSA tests. This is just to explain how to run tests even without Makefile. Makefile will be provided later on. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add tests for MSA FP max/min instructionsAleksandar Markovic8-0/+1240
Add tests for MSA FP max/min instructions. This includes following instructions: * FMAX.W - float maximum (words) * FMAX.D - float maximum (doublewords) * FMAX_A.W - float maximum absolute (words) * FMAX_A.D - float maximum absolute (doublewords) * FMIN.W - float minimum (words) * FMIN.D - float minimum (doublewords) * FMIN_A.W - float minimum absolute (words) * FMIN_A.D - float minimum absolute (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add utility function reset_msa_registers()Aleksandar Markovic227-4/+504
Add function reset_msa_registers() and utilize it in each MSA test. This is needed to ensure independency of test results on the state of MSA registers before test execution. This also allows for correction of tests for VSHF* instructions, that are now independent on the previous state of MSA registers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Move four tests to a better locationAleksandar Markovic4-0/+0
Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory to "fixed-point multiply" directory, since they do not operate on integers, but on fixed point numbers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Add tests for MSA shift instructionsAleksandar Markovic20-0/+3060
Add tests for MSA shift instructions. This includes following instructions: * SLL.B - shift left logical (bytes) * SLL.H - shift left logical (halfwords) * SLL.W - shift left logical (words) * SLL.D - shift left logical (doublewords) * SRA.B - shift right arithmetic (bytes) * SRA.H - shift right arithmetic (halfwords) * SRA.W - shift right arithmetic (words) * SRA.D - shift right arithmetic (doublewords) * SRAR.B - shift right arithmetic rounded (bytes) * SRAR.H - shift right arithmetic rounded (halfwords) * SRAR.W - shift right arithmetic rounded (words) * SRAR.D - shift right arithmetic rounded (doublewords) * SRL.B - shift right logical (bytes) * SRL.H - shift right logical (halfwords) * SRL.W - shift right logical (words) * SRL.D - shift right logical (doublewords) * SRLR.B - shift right logical rounded (bytes) * SRLR.H - shift right logical rounded (halfwords) * SRLR.W - shift right logical rounded (words) * SRLR.D - shift right logical rounded (doublewords) Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07tests/tcg: target/mips: Amend and rearrange MSA wrappersAleksandar Markovic1-160/+300
Amend and rearrange MSA wrappers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07target/mips: Unroll loops in helpers for MSA logic instructionsAleksandar Markovic1-4/+40
Unroll loops in helpers for MSA logic instructions for better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07target/mips: Outline places for future MSA helpersAleksandar Markovic1-0/+461
Outline places for future MSA helpers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07egl-helpers: add modifier support to egl_dmabuf_import_texture()Gerd Hoffmann1-9/+25
Check and use QemuDmaBuf->modifier in egl_dmabuf_import_texture() for dmabuf imports. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20190529072144.26737-5-kraxel@redhat.com
2019-06-07egl-helpers: add modifier support to egl_get_fd_for_texture().Gerd Hoffmann3-6/+9
Add modifier parameter to egl_get_fd_for_texture(), to return the used modifier on dmabuf exports. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20190529072144.26737-4-kraxel@redhat.com
2019-06-07vfio/display: set dmabuf modifier fieldGerd Hoffmann1-0/+1
Fill the new QemuDmaBuf->modifier field properly from plane info. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Alex Williamson <alex.williamson@redhat.com> Message-id: 20190529072144.26737-3-kraxel@redhat.com
2019-06-07console: add dmabuf modifier field.Gerd Hoffmann1-0/+1
dmabufs can have a format modifier (DRM_FORMAT_MOD_*) which is used for tiled layouts for example. Add a field to QemuDmaBuf so we can carry around that information. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20190529072144.26737-2-kraxel@redhat.com
2019-06-07ui/curses: Fix build with -m32Max Reitz1-4/+4
wchar_t may resolve to be an unsigned long on 32-bit architectures. Using the %x conversion specifier will then give a compiler warning: ui/curses.c: In function ‘get_ucs’: ui/curses.c:492:49: error: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘wchar_t’ {aka ‘long int’} [-Werror=format=] 492 | fprintf(stderr, "Could not convert 0x%04x " | ~~~^ | | | unsigned int | %04lx 493 | "from wchar_t to a multibyte character: %s\n", 494 | wch, strerror(errno)); | ~~~ | | | wchar_t {aka long int} ui/curses.c:504:49: error: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘wchar_t’ {aka ‘long int’} [-Werror=format=] 504 | fprintf(stderr, "Could not convert 0x%04x " | ~~~^ | | | unsigned int | %04lx 505 | "from a multibyte character to UCS-2 : %s\n", 506 | wch, strerror(errno)); | ~~~ | | | wchar_t {aka long int} Fix this by casting the wchar_t value to an unsigned long and using %lx as the conversion specifier. Fixes: b7b664a4fe9a955338f2e11a0f7433b29c8cbad0 Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Message-id: 20190527142540.23255-1-mreitz@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-06-06target/mips: Fix block-comment-related issues in msa_helper.cAleksandar Markovic1-15/+27
Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06target/mips: Fix space-related format issues in msa_helper.cAleksandar Markovic1-14/+14
Fix space-related format issues reported by checkpatch in file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06Merge remote-tracking branch ↵Peter Maydell19-40/+28
'remotes/vivier2/tags/trivial-branch-pull-request' into staging Trivial fixes 06/06/2019 # gpg: Signature made Thu 06 Jun 2019 12:05:50 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: hw/watchdog/wdt_i6300esb: Use DEVICE() macro to access DeviceState.qdev hw/scsi: Use the QOM BUS() macro to access BusState.qbus hw/sd: Use the QOM BUS() macro to access BusState.qbus hw/audio/ac97: Use the QOM DEVICE() macro to access DeviceState.qdev hw/vfio/pci: Use the QOM DEVICE() macro to access DeviceState.qdev hw/usb-storage: Use the QOM DEVICE() macro to access DeviceState.qdev hw/isa: Use the QOM DEVICE() macro to access DeviceState.qdev hw/s390x/event-facility: Use the QOM BUS() macro to access BusState.qbus hw/pci-bridge: Use the QOM BUS() macro to access BusState.qbus hw/scsi/vmw_pvscsi: Use qbus_reset_all() directly docs/devel/build-system: Update an example test: Fix make target check-report.tap util: Adjust qemu_guest_getrandom_nofail for Coverity vhost: fix incorrect print type migration: fix a typo hw/rdma: Delete unused headers inclusion Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-06Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell37-164/+261
virtio, pci, pc: cleanups, features stricter rules for acpi tables: we now fail on any difference that isn't whitelisted. vhost-scsi migration. some cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 05 Jun 2019 20:55:04 BST # gpg: using RSA key 281F0DB8D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: bios-tables-test: ignore identical binaries tests: acpi: add simple arm/virt testcase tests: add expected ACPI tables for arm/virt board bios-tables-test: list all tables that differ vhost-scsi: Allow user to enable migration vhost-scsi: Add VMState descriptor vhost-scsi: The vhost backend should be stopped when the VM is not running bios-tables-test: add diff allowed list vhost: fix memory leak in vhost_user_scsi_realize vhost: fix incorrect print type vhost: remove the dead code docs: smbios: remove family=x from type2 entry description pci: Fold pci_get_bus_devfn() into its sole caller pci: Make is_bridge a bool pcie: Simplify pci_adjust_config_limit() acpi: pci: use build_append_foo() API to construct MCFG hw/acpi: Consolidate build_mcfg to pci.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-06Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-4/+9
* Fix pr-manager-helper (Markus) # gpg: Signature made Wed 05 Jun 2019 15:15:34 BST # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: vl: Document why objects are delayed vl: Fix -drive / -blockdev persistent reservation management Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-06hw/watchdog/wdt_i6300esb: Use DEVICE() macro to access DeviceState.qdevPhilippe Mathieu-Daudé1-1/+1
Rather than looking inside the definition of a DeviceState with "s->qdev", use the QOM prefered style: "DEVICE(s)". This patch was generated using the following Coccinelle script: // Use DEVICE() macros to access DeviceState.qdev @use_device_macro_to_access_qdev@ expression obj; identifier dev; @@ -&obj->dev.qdev +DEVICE(obj) Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190528164020.32250-11-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-06hw/scsi: Use the QOM BUS() macro to access BusState.qbusPhilippe Mathieu-Daudé3-4/+4
Rather than looking inside the definition of a BusState with "s->bus.qbus", use the QOM prefered style: "BUS(&s->bus)". This patch was generated using the following Coccinelle script: // Use BUS() macros to access BusState.qbus @use_bus_macro_to_access_qbus@ expression obj; identifier bus; @@ -&obj->bus.qbus +BUS(&obj->bus) Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190528164020.32250-3-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-06Merge remote-tracking branch ↵Peter Maydell6-23/+246
'remotes/juanquintela/tags/migration-pull-request' into staging Migration Pull request # gpg: Signature made Wed 05 Jun 2019 12:52:06 BST # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/migration-pull-request: migratioin/ram: leave RAMBlock->bmap blank on allocating migration-test: Add a test for fd protocol migration: Fix fd protocol for incoming defer migration/ram.c: multifd_send_state->count is not really used migration/ram.c: MultiFDSendParams.sem_sync is not really used Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-06hw/sd: Use the QOM BUS() macro to access BusState.qbusPhilippe Mathieu-Daudé2-2/+2
Rather than looking inside the definition of a BusState with "s->bus.qbus", use the QOM prefered style: "BUS(&s->bus)". This patch was generated using the following Coccinelle script: // Use BUS() macros to access BusState.qbus @use_bus_macro_to_access_qbus@ expression obj; identifier bus; @@ -&obj->bus.qbus +BUS(&obj->bus) Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20190528164020.32250-6-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
generated by cgit v1.1 at 2024-11-03 16:46:58 +0000