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authorDavid Hildenbrand <david@redhat.com>2019-05-28 20:46:57 +0200
committerDavid Hildenbrand <david@redhat.com>2019-06-07 14:53:25 +0200
commitec8e23e37f80072a67ad409e6cdf67b65bb19eef (patch)
tree85cc5cd8a0357795fb86087a4805bd861a308c90
parent13b0228f77ffa14a0f82bd8a9d0fd5859b0d6a7d (diff)
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s390x: Align vector registers to 16 bytes
11e2bfef7990 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store") revealed that the vregs are not aligned to 16 bytes. Align them to 16 bytes, to avoid segfault'ing on x86. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
-rw-r--r--target/s390x/cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7305cac..1bed12b 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -66,7 +66,7 @@ struct CPUS390XState {
* The floating point registers are part of the vector registers.
* vregs[0][0] -> vregs[15][0] are 16 floating point registers
*/
- CPU_DoubleU vregs[32][2]; /* vector registers */
+ CPU_DoubleU vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
uint32_t aregs[16]; /* access registers */
uint8_t riccb[64]; /* runtime instrumentation control */
uint64_t gscb[4]; /* guarded storage control */