diff options
| author | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-06-06 18:27:12 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2019-06-06 21:06:33 +0200 |
| commit | 7cc8a7220de39d77894edcb376378f280ec9c4c2 (patch) | |
| tree | 7669dbdbc6e4bb9b5dc6831c609bc801173a1d92 | |
| parent | de1700d316c18edcca0d5264b69863edb8c9bf0d (diff) | |
| download | qemu-7cc8a7220de39d77894edcb376378f280ec9c4c2.zip qemu-7cc8a7220de39d77894edcb376378f280ec9c4c2.tar.gz qemu-7cc8a7220de39d77894edcb376378f280ec9c4c2.tar.bz2 | |
target/mips: Fix block-comment-related issues in msa_helper.c
Fix block-comment-related issues reported by checkpatch for file
msa_helper.c.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
| -rw-r--r-- | target/mips/msa_helper.c | 42 |
1 files changed, 27 insertions, 15 deletions
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index eacb5a4..851450c 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1975,8 +1975,10 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) c &= ~FP_UNDERFLOW; } - /* Reciprocal operations set only Inexact when valid and not - divide by zero */ + /* + * Reciprocal operations set only Inexact when valid and not + * divide by zero + */ if ((action & RECIPROCAL_INEXACT) && (c & (FP_INVALID | FP_DIV0)) == 0) { c = FP_INEXACT; @@ -1985,15 +1987,19 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) cause = c & enable; /* all current enabled exceptions */ if (cause == 0) { - /* No enabled exception, update the MSACSR Cause - with all current exceptions */ + /* + * No enabled exception, update the MSACSR Cause + * with all current exceptions + */ SET_FP_CAUSE(env->active_tc.msacsr, (GET_FP_CAUSE(env->active_tc.msacsr) | c)); } else { /* Current exceptions are enabled */ if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) { - /* Exception(s) will trap, update MSACSR Cause - with all enabled exceptions */ + /* + * Exception(s) will trap, update MSACSR Cause + * with all enabled exceptions + */ SET_FP_CAUSE(env->active_tc.msacsr, (GET_FP_CAUSE(env->active_tc.msacsr) | c)); } @@ -3059,9 +3065,11 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee = 1; MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16); @@ -3617,9 +3625,11 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee = 1; MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32); @@ -3651,9 +3661,11 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, switch (df) { case DF_WORD: for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { - /* Half precision floats come in two formats: standard - IEEE and "ARM" format. The latter gains extra exponent - range by omitting the NaN/Inf encodings. */ + /* + * Half precision floats come in two formats: standard + * IEEE and "ARM" format. The latter gains extra exponent + * range by omitting the NaN/Inf encodings. + */ flag ieee = 1; MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32); |