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-rw-r--r--target/microblaze/cpu.c9
-rw-r--r--target/microblaze/cpu.h5
-rw-r--r--target/microblaze/helper.c4
-rw-r--r--target/microblaze/mmu.c30
-rw-r--r--target/microblaze/mmu.h7
5 files changed, 30 insertions, 25 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index b9bb7f0..fde646a 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -135,10 +135,6 @@ static void mb_cpu_reset(DeviceState *dev)
#else
mb_cpu_write_msr(env, 0);
mmu_init(&env->mmu);
- env->mmu.c_mmu = 3;
- env->mmu.c_mmu_tlb_access = 3;
- env->mmu.c_mmu_zones = 16;
- env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
#endif
}
@@ -232,6 +228,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
16 << 17);
+ cpu->cfg.mmu = 3;
+ cpu->cfg.mmu_tlb_access = 3;
+ cpu->cfg.mmu_zones = 16;
+ cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
+
mcc->parent_realize(dev, errp);
}
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index ef96f2f..b54f99d 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -295,6 +295,8 @@ struct CPUMBState {
typedef struct {
char *version;
+ uint64_t addr_mask;
+
uint32_t base_vectors;
uint32_t pvr_user2;
uint32_t pvr_regs[13];
@@ -304,6 +306,9 @@ typedef struct {
uint8_t use_hw_mul;
uint8_t pvr_user1;
uint8_t pvr;
+ uint8_t mmu;
+ uint8_t mmu_tlb_access;
+ uint8_t mmu_zones;
bool stackprot;
bool use_barrel;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index c9f236c..3d6ce1b 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -64,7 +64,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return true;
}
- hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx);
+ hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
if (likely(hit)) {
uint32_t vaddr = address & TARGET_PAGE_MASK;
uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
@@ -240,7 +240,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
unsigned int hit;
if (mmu_idx != MMU_NOMMU_IDX) {
- hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
+ hit = mmu_translate(cpu, &lu, addr, 0, 0);
if (hit) {
vaddr = addr & TARGET_PAGE_MASK;
paddr = lu.paddr + vaddr - lu.vaddr;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 0546cfd..1dbbb27 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -73,9 +73,10 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
}
/* rw - 0 = read, 1 = write, 2 = fetch. */
-unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
+unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
{
+ MicroBlazeMMU *mmu = &cpu->env.mmu;
unsigned int i, hit = 0;
unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
uint64_t tlb_tag, tlb_rpn, mask;
@@ -114,13 +115,13 @@ unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
t0 &= 0x3;
- if (tlb_zsel > mmu->c_mmu_zones) {
+ if (tlb_zsel > cpu->cfg.mmu_zones) {
qemu_log_mask(LOG_GUEST_ERROR,
"tlb zone select out of range! %d\n", tlb_zsel);
t0 = 1; /* Ignore. */
}
- if (mmu->c_mmu == 1) {
+ if (cpu->cfg.mmu == 1) {
t0 = 1; /* Zones are disabled. */
}
@@ -157,7 +158,7 @@ unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
tlb_rpn = d & TLB_RPN_MASK;
lu->vaddr = tlb_tag;
- lu->paddr = tlb_rpn & mmu->c_addr_mask;
+ lu->paddr = tlb_rpn & cpu->cfg.addr_mask;
lu->size = tlb_size;
lu->err = ERR_HIT;
lu->idx = i;
@@ -175,10 +176,11 @@ done:
/* Writes/reads to the MMU's special regs end up here. */
uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
{
+ MicroBlazeCPU *cpu = env_archcpu(env);
unsigned int i;
uint32_t r = 0;
- if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
+ if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {
qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return 0;
}
@@ -191,7 +193,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
/* Reads to HI/LO trig reads from the mmu rams. */
case MMU_R_TLBLO:
case MMU_R_TLBHI:
- if (!(env->mmu.c_mmu_tlb_access & 1)) {
+ if (!(cpu->cfg.mmu_tlb_access & 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Invalid access to MMU reg %d\n", rn);
return 0;
@@ -204,7 +206,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
break;
case MMU_R_PID:
case MMU_R_ZPR:
- if (!(env->mmu.c_mmu_tlb_access & 1)) {
+ if (!(cpu->cfg.mmu_tlb_access & 1)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Invalid access to MMU reg %d\n", rn);
return 0;
@@ -227,12 +229,14 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
+ MicroBlazeCPU *cpu = env_archcpu(env);
uint64_t tmp64;
unsigned int i;
+
qemu_log_mask(CPU_LOG_MMU,
"%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]);
- if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
+ if (cpu->cfg.mmu < 2 || !cpu->cfg.mmu_tlb_access) {
qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
return;
}
@@ -258,7 +262,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);
break;
case MMU_R_ZPR:
- if (env->mmu.c_mmu_tlb_access <= 1) {
+ if (cpu->cfg.mmu_tlb_access <= 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"Invalid access to MMU reg %d\n", rn);
return;
@@ -272,7 +276,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
env->mmu.regs[rn] = v;
break;
case MMU_R_PID:
- if (env->mmu.c_mmu_tlb_access <= 1) {
+ if (cpu->cfg.mmu_tlb_access <= 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"Invalid access to MMU reg %d\n", rn);
return;
@@ -292,14 +296,14 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
MicroBlazeMMULookup lu;
int hit;
- if (env->mmu.c_mmu_tlb_access <= 1) {
+ if (cpu->cfg.mmu_tlb_access <= 1) {
qemu_log_mask(LOG_GUEST_ERROR,
"Invalid access to MMU reg %d\n", rn);
return;
}
- hit = mmu_translate(&env->mmu, &lu,
- v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
+ hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
+ 0, cpu_mmu_index(env, false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else {
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index c1feb81..7d0fbb8 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -70,11 +70,6 @@ typedef struct {
uint8_t tids[TLB_ENTRIES];
/* Control flops. */
uint32_t regs[3];
-
- int c_mmu;
- int c_mmu_tlb_access;
- int c_mmu_zones;
- uint64_t c_addr_mask; /* Mask to apply to physical addresses. */
} MicroBlazeMMU;
typedef struct {
@@ -88,7 +83,7 @@ typedef struct {
} err;
} MicroBlazeMMULookup;
-unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
+unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
generated by cgit v1.1 at 2024-12-29 01:09:28 +0000