diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/hppa/cpu.h | 19 | ||||
| -rw-r--r-- | target/hppa/helper.c | 2 | ||||
| -rw-r--r-- | target/hppa/mem_helper.c | 16 | ||||
| -rw-r--r-- | target/hppa/translate.c | 9 |
4 files changed, 29 insertions, 17 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 75c5c0c..fa13694 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -30,11 +30,22 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL -#define MMU_KERNEL_IDX 0 -#define MMU_USER_IDX 3 -#define MMU_PHYS_IDX 4 +#define MMU_KERNEL_IDX 11 +#define MMU_PL1_IDX 12 +#define MMU_PL2_IDX 13 +#define MMU_USER_IDX 14 +#define MMU_PHYS_IDX 15 + +#define PRIV_TO_MMU_IDX(priv) (MMU_KERNEL_IDX + (priv)) +#define MMU_IDX_TO_PRIV(mmu_idx) ((mmu_idx) - MMU_KERNEL_IDX) + #define TARGET_INSN_START_EXTRA_WORDS 1 +/* No need to flush MMU_PHYS_IDX */ +#define HPPA_MMU_FLUSH_MASK \ + (1 << MMU_KERNEL_IDX | 1 << MMU_PL1_IDX | \ + 1 << MMU_PL2_IDX | 1 << MMU_USER_IDX) + /* Hardware exceptions, interrupts, faults, and traps. */ #define EXCP_HPMC 1 /* high priority machine check */ #define EXCP_POWER_FAIL 2 @@ -233,7 +244,7 @@ static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) return MMU_USER_IDX; #else if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return env->iaoq_f & 3; + return PRIV_TO_MMU_IDX(env->iaoq_f & 3); } return MMU_PHYS_IDX; /* mmu disabled */ #endif diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 74b8747..a8d3f45 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -71,7 +71,7 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) /* If PSW_P changes, it affects how we translate addresses. */ if ((psw ^ old_psw) & PSW_P) { #ifndef CONFIG_USER_ONLY - tlb_flush_by_mmuidx(env_cpu(env), 0xf); + tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); #endif } } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 5046cc8..46c3dca 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -50,8 +50,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent) trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa); for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) { - /* Do not flush MMU_PHYS_IDX. */ - tlb_flush_page_by_mmuidx(cs, addr, 0xf); + tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK); } memset(ent, 0, sizeof(*ent)); @@ -74,7 +73,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot) { hwaddr phys; - int prot, r_prot, w_prot, x_prot; + int prot, r_prot, w_prot, x_prot, priv; hppa_tlb_entry *ent; int ret = -1; @@ -98,9 +97,10 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, phys = ent->pa + (addr & ~TARGET_PAGE_MASK); /* Map TLB access_rights field to QEMU protection. */ - r_prot = (mmu_idx <= ent->ar_pl1) * PAGE_READ; - w_prot = (mmu_idx <= ent->ar_pl2) * PAGE_WRITE; - x_prot = (ent->ar_pl2 <= mmu_idx && mmu_idx <= ent->ar_pl1) * PAGE_EXEC; + priv = MMU_IDX_TO_PRIV(mmu_idx); + r_prot = (priv <= ent->ar_pl1) * PAGE_READ; + w_prot = (priv <= ent->ar_pl2) * PAGE_WRITE; + x_prot = (ent->ar_pl2 <= priv && priv <= ent->ar_pl1) * PAGE_EXEC; switch (ent->ar_type) { case 0: /* read-only: data page */ prot = r_prot; @@ -335,13 +335,13 @@ void HELPER(ptlbe)(CPUHPPAState *env) { trace_hppa_tlb_ptlbe(env); memset(env->tlb, 0, sizeof(env->tlb)); - tlb_flush_by_mmuidx(env_cpu(env), 0xf); + tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); } void cpu_hppa_change_prot_id(CPUHPPAState *env) { if (env->psw & PSW_P) { - tlb_flush_by_mmuidx(env_cpu(env), 0xf); + tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); } } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d66fcb3..e3af668 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4057,14 +4057,15 @@ static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->tb_flags = ctx->base.tb->flags; #ifdef CONFIG_USER_ONLY - ctx->privilege = MMU_USER_IDX; + ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX); ctx->mmu_idx = MMU_USER_IDX; - ctx->iaoq_f = ctx->base.pc_first | MMU_USER_IDX; - ctx->iaoq_b = ctx->base.tb->cs_base | MMU_USER_IDX; + ctx->iaoq_f = ctx->base.pc_first | ctx->privilege; + ctx->iaoq_b = ctx->base.tb->cs_base | ctx->privilege; ctx->unalign = (ctx->tb_flags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN); #else ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); + ctx->mmu_idx = (ctx->tb_flags & PSW_D ? + PRIV_TO_MMU_IDX(ctx->privilege) : MMU_PHYS_IDX); /* Recover the IAOQ values from the GVA + PRIV. */ uint64_t cs_base = ctx->base.tb->cs_base; |