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-rw-r--r--target/riscv/csr.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 49566d3..7948188 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -192,6 +192,11 @@ static RISCVException cfi_ss(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ /* If ext implemented, M-mode always have access to SSP CSR */
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ }
+
/* if bcfi not active for current env, access to csr is illegal */
if (!cpu_get_bcfien(env)) {
#if !defined(CONFIG_USER_ONLY)
@@ -4297,7 +4302,7 @@ static RISCVException rmw_sctrdepth(CPURISCVState *env, int csrno,
}
/* Update sctrstatus.WRPTR with a legal value */
- depth = 16 << depth;
+ depth = 16ULL << depth;
env->sctrstatus =
env->sctrstatus & (~SCTRSTATUS_WRPTR_MASK | (depth - 1));
}