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-rw-r--r--target/riscv/cpu.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7aa041f..a5aa3a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2699,7 +2699,6 @@ static const Property riscv_cpu_properties[] = {
* it with -x and default to 'false'.
*/
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
- DEFINE_PROP_END_OF_LIST(),
};
#if defined(TARGET_RISCV64)